5

LTC1663

≤ 5.5V. Also used as the reference voltage input when the

AD0 (Pin 6): Slave Address Select Bit 0. Tie this pin to

LTC1663’s slave address.

GND (Pin 7, Pin 2 on SOT-23): System Ground.

rail-to-rail DAC output.

SDA (Pin 1, Pin 1 on SOT-23): Serial Data Bidirectional

Pin. Data is shifted into the SDA pin and acknowledged by

the SDA pin. High impedance pin while data is shifted in.

Open-drain N-channel output during acknowledgment.

AD1 (Pin 2): Slave Address Select Bit 1. Tie this pin to

LTC1663’s slave address.

AD2 (Pin 3): Slave Address Select Bit 2. Tie this pin to

LTC1663’s slave address.

SCL (Pin 4, Pin 5 on SOT-23): Serial Clock Input Pin. Data

is shifted into the SDA pin at the rising edges of the clock.

This high impedance pin requires a pull-up resistor or

zero. The INL error at a given input code is calculated as

follows:

the given input code.

Least Significant Bit (LSB): The ideal voltage difference

between two successive codes.

Resolution (n): Defines the number of DAC output states

imply linearity.

output when the DAC is loaded with all zeros. A single

supply DAC can have a true negative offset, but the output

cannot go below zero (see Applications Information).

For this reason, single supply DAC offset is measured at

the lowest code that guarantees the output will be greater

than zero.

Differential Nonlinearity (DNL): The difference between

the measured change and the ideal 1LSB change for any

two adjacent codes. The DNL error between any two codes

is calculated as follows:

DNL = (

Where

two adjacent codes.

Digital Feedthrough: The glitch that appears at the analog

output caused by AC coupling from the digital inputs when

they change state. The area of the glitch is specified in

(nV)(sec).

Full-Scale Error (FSE): The deviation of the actual full-

scale voltage from ideal. FSE includes the effects of offset

and gain errors (see Applications Information).

Integral Nonlinearity (INL): The deviation from a straight

line passing through the endpoints of the DAC transfer

curve (Endpoint INL). Because the output cannot go below

zero, the linearity is measured between full scale and the

lowest code that guarantees the output will be greater than