8

LTC1665/LTC1660

TI I G DIAGRA

Figure 1

OPERATIO

Transfer Function

The transfer function is

V

k

V

for the LTC

V

k

V

for the LTC

OUT IDEAL

REF

OUT IDEAL

REF

()

()

= 







= 







256

1665

1024

1660

where k is the decimal equivalent of the binary DAC input

Power-On Reset

The LTC1665 clears the outputs to zero scale when power

is first applied, making system initialization consistent and

repeatable.

Power Supply Sequencing

The voltage at REF (Pin 6) should be kept within the range

– 0.2V

Ratings). Particular care should be taken to observe these

limits during power supply turn-on and turn-off sequences,

Serial Interface

Referring to Figure 2a (2b): With CS/LD held low, data on

positive edge of SCK. The 4-bit DAC address, A3-A0, is

loaded first (see Table 2), then the 8-bit (10-bit) input

code, D7-D0 (D9-D0), ordered MSB-to-LSB in each case.

Four (two) don’t-care bits, X3-X0 (X1-X0), are loaded last.

When the full 16-bit input word has been shifted in, CS/LD

is pulled high, loading the DAC register with the word and

causing the addressed DAC output(s) to update. The

clock is disabled internally when CS/LD is high. Note: SCK

must be low before CS/LD is pulled low.

The buffered serial output of the shift register is available

Multiple LTC1665/LTC1660’s can be controlled from a

using the included “daisy-chain” facility. A series of

m

register. The SCK and CS/LD signals are common to all

CS/LD

SCK

A3

A3

A3

A2

A2

X1

A1

X0

1665/60 F01

A1

X1

X0