9

LTC1665/LTC1660

Figure 2a. LTC1665 Register Loading Sequence

OPERATIO

Table 1a. LTC1665 Input Word

SCK

CS/LD

A3

A2

INPUT CODE

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

X3

X2

X1

X0

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

X3

X2

X1

X0

A3

1665/60 F02a

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

(ENABLE CLK)

(UPDATE OUTPUT)

ADDRESS/CONTROL

DON’T CARE

SCK

CS/LD

A3

A2

INPUT CODE

DON’T CARE

A1

A0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

X1

X0

A3

A2

A1

A0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

X1

X0

A3

1665/60 F02b

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

(ENABLE CLK)

(UPDATE OUTPUT)

ADDRESS/CONTROL

Figure 2b. LTC1660 Register Loading Sequence

A3 A2 A1

Address/Control

A0 D7 D6 D5 D4 D3 D2 D1 D0 X3

X1 X0

X2

Don’t Care

Input Code

A3 A2 A1

Address/Control

A0 D9 D8 D7 D6 D5 D4 D3 D2 D1

X1 X0

D0

Input Code

Don’t

Care

Table 1b. LTC1660 Input Word

chips in the chain. In use, CS/LD is held low while

m

then pulled high, updating all of them simultaneously.

Sleep Mode

instruction (see Table 2). In this mode, the digital interface

stays active while the analog circuits are disabled; static

power consumption is thus virtually eliminated. The refer-

ence input and analog outputs are set in a high impedance