PROGRAMMABLE DIGITAL DELAY TIMER

February 1998

FEATURES:

• Programmable Delay from 6 ms to "Infinity"

• Can be Cascaded for Sequential Events or Extended Delay

• On Chip Oscillator or External Clock time base

• High Noise Immunity

• LS7210 (DIP), LS7210-S (SOIC)-See Figure 1

DESCRIPTION:

The LS7210 is a monolithic MOS integrated circuit programmable

digital timer that can generate a delay in the range of 6ms to infinity.

The delay is programmed by 5 binary weighted input bits in combina-

tion with the time base provided. The chip can be operated in four

different modes: Delayed Operate, Delayed Release, Dual Delay

and One Shot. These modes are selected by the control inputs A

and B.

INPUT/OUTPUT DESCRIPTION:

OSCILLATOR Input (Pin 5)

The frequency of the internal oscillator is set by an RC network con-

nected to the OSC input, as shown in Figure 2. The nominal os-

cillator frequency, f, at room temperature is given by f

≈1/RC where R

values range from a minimum of 47K

Ω to a maximum 3MΩ.

NOTE: Oscillation accuracy from chip to chip for a fixed value of RC,

is + 10%. (Parts can supplied to tighter tolerances.)

EXTERNAL CLOCK Input (Pin 6)

If the internal oscillator is not used, the chip can be driven by an ex-

ternal clock applied to this input.

CLOCK SELECT Input (Pin 4)

The internal oscillator or the external clock is selected by the proper

logic level applied to this input. A logic 1 selects the external clock

and logic 0 selects the internal oscillator. (See Note 1)

TRIGGER Input (Pin 3)

A positive or a negative transition at the trigger input initiates a delay

in turning on or off the output. A negative transition always turns on

the output with or without delay depending on the selected mode. A

positive transition at the trigger input always turns off the output (with

the exception of one-shot mode) with or without delay depending on

the selected mode. The delay is a function of the time base fre-

quency and the weighting factor programmed at the weighting bit in-

puts. The trigger input is clocked into the input latch with the neg-

ative edge of the selected time base clock. All timings begin after the

latch has been set up. (See Note 1)

WEIGHTING FACTOR Inputs, WB0-WB4 (Pins 12-8)

A delay from the trigger input to the output is programmed by ap-

plying 1's complement binary weighted numbers at these 5 inputs.

(See Note 1) The exact equation for the delay is:

Delay =

(1 + 1, 023N)

f = Oscillation Frequency

f

N = Weighting Factor

TABLE 1. WEIGHTING BITS ASSIGNMENTS

INPUTS

VALUE

WB0

1

WB1

2

WB2

4

WB3

8

WB4

16

Example: For a weighting factor of 25, inputs WB4, WB3, and

WB0 should be programmed to logic 0.

MODE SELECT Inputs A, B (Pins 2, 1)

The chip can be programmed to operate in four different modes

by applying the logic levels to inputs A and B as indicated in

Table 2. The mode select inputs are clocked into the input latch-

es with the negative edge of the time base clock. These inputs

should not be changed while a delay timing is in progress. (See

Note 1)

TABLE 2. MODE SELECTION

CONTROL

MODE

A

B

1

1

Dual Delay

1

0

Delayed Release

0

1

Delayed Operate

0

0

One Shot

OUT Output (Pin 13)

The output is an open drain FET. To obtain proper switching of

the output between Logic 0 and 1 levels, an external pull down re-

source, no such pull down is needed. The output is logically in-

verted with respect to the trigger input.

Supply voltage positive, negative terminals.

NOTE 1: These inputs have internal pullup resistors.

1

2

3

4

5

6

7

14

13

12

11

10

9

8

B

A

TRIGGER

CLOCK SELECT

OSCILLATOR

EXTERNAL CLOCK

OUT

WB0

WB1

WB2

WB3

WB4

FIGURE 1

PIN ASSIGNMENT - TOP VIEW

7210-041700-1

LSI/CSI

LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747

(631) 271-0400 FAX (631) 271-0405

LS7210

UL

®

A3800