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LS7210 数据表(PDF) 2 Page - LSI Computer Systems |
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LS7210 数据表(HTML) 2 Page - LSI Computer Systems |
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2 / 4 page ![]() 7210-020298-2 DELAYED RELEASE MODE This mode causes a retriggerable delay in turning off the output whenever there is a positive transition at the trigger input. The out- put is turned on without delay in response to a negative transition at the trigger input. ONE-SHOT MODE In this mode, the chip functions like a retriggerable monostable multi-vibrator. The output is turned on whenever there is a negative transition at the trigger input. At the end of the programmed delay, the output is turned off automatically. If there is a negative transition at the trigger input before the delay is over, the delay is restarted. A positive transition at the trigger input has no effect on the output in this mode. NOTE: In One-Shot mode, the TRIGGER input must be held at logic 1 during a power-up. ABSOLUTE MAXIMUM RATINGS: (All voltages referenced to VDD) SYMBOL VALUE UNIT DC Supply Voltage VSS +18 V Voltage (Any Pin) VIN 0 to VSS+.3 V Operating Temperature TA -25 to +70 °C Storage Temperature TSTG -65 to +150 °C DC ELECTRICAL CHARACERISTICS: (-25°C ≤TA ≤+70°C unless otherwise specified. All voltages referenced to VDD) PARAMETER SYMBOL MIN MAX UNIT CONDITION Suppy Voltage VSS +4.75 +15.0 V Supply Current ISS - 3.0 mA VSS = +15V, output off Trigger Input Logic 1 VTH VSS -1 VSS V - Logic 0 VTL 0 .2VSS V - All Other Inputs Logic 1 VIH .8VSS VSS V - Logic 0 VIL 0 .2VSS V - Output Source Current Io +1.0 - mA VSS = + 5V for Vo = Vss - 1V Io +2.8 - mA VSS = +10V Io +4.2 - mA VSS = +15V SWITCHING CHARACTERISTICS: (See Figure 4) PARAMETER SYMBOL MIN MAX UNIT Oscillator Frequency fOSC - 50 KHz External Clock Frequency fext DC 160 KHz External Clock, Positive Pulse Width tH 3 - µs External Clock, Negative Pulse Width tL 3 - µs A,B and Trigger Input Set-Up Time tS - 300 ns Time-base Clock to Output Delay (turn-on delay in Delayed Release mode and turn-off delay in Delayed Operate mode) tnd - 1 µs Time-base Clock to Output Delay at the End of Time Out tod - 1.6 µs Time-base Clock to Output Delay tsd - 600 ns (turn-on delay in One- Shot Mode) MODE DEFINITION TIMING DIAGRAM: (See Figure 3) DUAL DELAY MODE Thls is the Default Mode when the inputs A and B are left un- programmed. The function of the Dual Delay mode is to provide a time delay on both the turn-on and turn-off of the output. Once turned on, the output will remain on as long as the trigger input is Logic 0. Once turned off, the output will remain off as long as the trigger input is a logic 1. DELAYED OPERATE MODE This mode causes a retriggerable delay in turning the output on in re- sponse to a negative edge at the trigger input. The output is turned off without delay in response to a positive transition at the trigger in- put. |
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