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MAX1111EEE 数据表(PDF) 12 Page - Maxim Integrated Products |
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MAX1111EEE 数据表(HTML) 12 Page - Maxim Integrated Products |
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12 / 20 page ![]() Simple Software Interface Make sure the CPU’s serial interface runs in master mode so the CPU generates the serial clock. Choose a clock frequency from 50kHz to 500kHz. 1) Set up the control byte for external clock mode and call it TB1. TB1 should be of the format 1XXXXX11 binary, where the Xs denote the particular channel and conversion mode selected. 2) Use a general-purpose I/O line on the CPU to pull CS low. 3) Transmit TB1 and, simultaneously, receive a byte and call it RB1. Ignore RB1. 4) Transmit a byte of all zeros ($00 hex) and, simulta- neously, receive byte RB2. 5) Transmit a byte of all zeros ($00 hex) and, simulta- neously, receive byte RB3. 6) Pull CS high. Figure 7 shows the timing for this sequence. Bytes RB2 and RB3 contain the result of the conversion padded with two leading zeros and six trailing zeros. The total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. Make sure that the total conversion time does not exceed 1ms, to avoid excessive T/H droop. Digital Inputs CS, SCLK, and DIN can accept input signals up to 5.5V, regardless of the supply voltages. This allows the MAX1110/MAX1111 to accept digital inputs from both 3V and 5V systems. +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs 12 ______________________________________________________________________________________ SSTRB CS SCLK DIN DOUT 14 8 12 16 20 24 START SEL2 SEL1 SEL0 UNI/ BIP SGL/ DIF PD1 PD0 B7 B6 B5 B4 B3 B2 B1 B0 ACQUISITION (fSCLK = 500kHz) IDLE FILLED WITH ZEROS IDLE CONVERSION tACQ A/D STATE RB1 RB2 RB3 4 µs Figure 7. Single-Conversion Timing, External Clock Mode, 24 Clocks CS SCLK DOUT I/O SCK MISO +3V SS a) SPI CS SCLK DOUT CS SCK MISO +3V SS b) QSPI MAX1110 MAX1111 MAX1110 MAX1111 MAX1110 MAX1111 CS SCLK DOUT I/O SK SI c) MICROWIRE Figure 6. Common Serial-Interface Connections to the MAX1110/MAX1111 |
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