+2.7V, Low-Power, Multichannel,

Serial 8-Bit ADCs

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5

ns

100

Figure 1, external clock mode only,

ns

CS to SCLK Rise Setup

240

ns

20

200

ns

0

CONDITIONS

CS to SCLK Rise Hold

240

CS Fall to Output Enable

ns

240

CS Rise to Output Disable

CS Fall to SSTRB Output Enable

(Note 6)

Figure 2, external clock mode only,

ns

240

CS Rise to SSTRB Output

Disable (Note 6)

Figure 11, internal clock mode only

ns

0

SSTRB Rise to SCLK Rise

(Note 6)

ns

200

SCLK Pulse Width High

ns

200

SCLK Pulse Width Low

ns

240

SCLK Fall to SSTRB

ns

0

DIN to SCLK Hold

µs

1

Track/Hold Acquisition Time

ns

100

DIN to SCLK Setup

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

TIMING CHARACTERISTICS (Figures 8 and 9)

Note 1:

Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.

Note 2:

See

Typical Operating Characteristics.

Note 3:

Note 4:

On-channel grounded; sine wave applied to all off-channels.

Note 5:

Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.

Note 6:

Guaranteed by design. Not subject to production testing.

Note 7:

Note 8:

External load should not change during the conversion for specified accuracy.

Note 9:

External reference at 2.048V, full-scale input, 500kHz external clock.

Note 10: Measured as

Note 11: 1µF at REFOUT; internal reference settling to 0.5LSB.

ns

20

240

SCLK Fall to Output Data Valid

Figure 1,

MAX111_C/E

MAX111_M

External reference

20

Internal reference (Note 11)

µs

12

Wake-Up Time

ms