AFBR-810BZ datasheet(25/48 Pages) AVAGO

25 / 48 page

1. Memory Map Overview

The memory is structured as a single address, multiple

page approach after that in the XFP MSA and adapted

by QSFP MSA for multi-channel transceivers. Figure 27

presents an overview of the memory structure showing a

lower page (5ih) and two upper pages (00h and 01h). As

with XFP and QSFP, time sensitive, dynamic and/or high

interest information are contained in the base, i.e. lower,

page. Here the upper page 00h contains the serial id

Byte

Type Lower Memory Page 5ih

RO Identiﬁer

1-2

RO Status

3-27

RO Interrupt Flags: LOS, Fault, Monitor

28-39

RO Module Monitors

40-87

RO Channel Monitors

88-89

RO Elapsed Operating Time

90-105 RW Controls (Volatile)

106-118 RW Masks: LOS, Fault, Module Flags

119-126 RW Reserved

127

RW Upper Page Select Byte

Byte

Type Upper Memory Page 00h

Byte

Type Upper Memory Page 01h

128-129 RO Identiﬁers

128-175 RO Module Thresholds

130

RO Description: Power Supplies

176-223 RO Channel Thresholds

131

RO Description: Max Case Temp

224

RO Checksum

132-133 RO Description: Min/Max Signal Rate

225-243 RW Controls (Non-volatile)

134-137 RO Description: Wavelength

244-255 RW Masks: Channel Monitor Flags

138-143 RO Description: Supported Functions

144-151 RO Reserved

152-170 RO Vendor Information: Name & OUI

171-188 RO Vendor Information: PN & PN rev

189-204 RO Vendor Information: SN

205-212 RO Vendor Information: Date Code

213-222 RO Vendor Information: CLEI Code

223

RO Checksum

224-255 RO Vendor Speciﬁc

Figure 27. Two-Wire Serial Address 5ih Page Structure

information, again following the style of XFP and QSFP.

The 01h upper table contains static threshold information,

configuration controls and flag masks.

Unless otherwise stated all reserved bytes are coded 00h

and all reserved bits are coded 0b. Non-volatile read-

write bits are labeled RWn and volatile read-write bits are

labeled RWv.

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