HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR

S-T111 Series

Seiko Instruments Inc.

8



Standard Circuit

ON/OFF

VSS

VOUT

VIN

*1

*2

Input

Output

GND

Single GND

*2. A ceramic capacitor of 0.1

Figure 9

Caution The above connection diagram and constant will not guarantee successful operation.

Perform thorough evaluation using the actual application to set the constant.



Condition of Application

0.1

μF or more

0.1

μF or more

ESR of output capacitor:

10

Ω or less

Caution Generally a series regulator may cause oscillation, depending on the selection of external

parts. Check that no oscillation occurs with the application using the above capacitor.



The S-T111 Series requires an output capacitor between the VOUT pin and the VSS pin for phase

compensation. Operation is stabilized by a ceramic capacitor with an output capacitance of 0.1

μF or more in

the entire temperature range. When using an OS capacitor, a tantalum capacitor, or an aluminum electrolytic

capacitor, the capacitance must be 0.1

μF or more, and the ESR must be 10 Ω or less.

The value of the output overshoot or undershoot transient response varies depending on the value of the output

capacitor. The required capacitance of the input capacitor differs depending on the application.

output capacitor, perform sufficient evaluation, including evaluation of temperature characteristics, on the actual

device.