HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR

S-T111 Series

Seiko Instruments Inc.

13



Precautions

• Wiring patterns for the VIN pin, the VOUT pin and GND should be designed so that the impedance is

these pins should be as short as possible.

• Note that generally the output voltage may increase when a series regulator is used at low load current

(1.0 mA or less).

• Generally a series regulator may cause oscillation, depending on the selection of external parts. The

following conditions are recommended for S-T111 Series. However, be sure to perform sufficient

evaluation under the actual usage conditions for selection, including evaluation of temperature

characteristics.

1.0

μF or more

0.47

μF or more

Equivalent series resistance (ESR): 10

Ω or less

• The voltage regulator may oscillate when the impedance of the power supply is high and the input

capacitance is small or an input capacitor is not connected.

• Overshoot may occur in the output voltage momentarily if the voltage is rapidly raised at power-on or

when the power supply fluctuates. Sufficiently evaluate the output voltage at power-on with the actual

device.

• The application conditions for the input voltage, the output voltage, and the load current should not

exceed the package power dissipation.

• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in

electrostatic protection circuit.

• In determining the output current, attention should be paid to the output current value specified in Table

4 in “ Electrical Characteristics” and footnote *5 of the table.

• SII claims no responsibility for any disputes arising out of or in connection with any infringement by

products including this IC of patents owned by a third party.