TSI721 datasheet(39/68 Pages) IDT

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3. Electrical Characteristics > AC Timing Specifications

Tsi721 Datasheet

May 5, 2014

Formal Status

This document is confidential and is subject to an NDA.

Integrated Device Technology

1. SSC permits a +0, -5000 ppm modulation on the clock frequency at a modulation rate not to exceed 33 kHz.

2. Measurements at 5.0 Gbps require an oscilloscope with a bandwidth of >= 12.5 GHz, or equivalent, while measurements

made at 2.5 Gbps require a scope with at least 6.2 GHz of bandwidth. Measurements at 5.0 Gbps must deconvolve effects

of compliance test board to produce an effective measurement at Tx pins. 2.5 Gbps may be measured within 200 mils of Tx

device’s pins, although deconvolution is recommended. For measurement setup information, refer to Figure 4-23 and Figure

4-24 of PCI Express Base Specification (Rev. 2.1). At least 106 UI of data must be acquired.

3. Transmitter jitter is measured by driving the Transmitter under test with a low jitter “ideal” clock and connecting the DUT to

a reference load.

4. Transmitter raw jitter data must be convolved with a filtering function that represents the worst case CDR tracking BW.

2.5 Gbps use different filter functions that are defined in Figure 4-21 of PCI Express Base Specification (Rev. 2.1). After the

convolution process has been applied, the center of the resulting eye must be determined and used as a reference point for

obtaining eye voltage and margins.

5. VTX-AC-CM-PP and VTX-AC-CM-P are defined in Section 4.3.3.7 of PCI Express Base Specification (Rev. 2.1).

Measurement is made over at least 106 UI.

6. The Tx PLL Bandwidth must lie between the minimum and maximum ranges displayed in the table. PLL peaking must lie

below the value listed. Note: the PLL B/W extends from zero up to the value(s) specified in the table.

7. Measurements are made for both common mode and differential return loss. The DUT must be powered up and DC isolated,

and its data+/data- outputs must be in the low-Z state at a static value.

TTX-IDLE-SET-TO

-IDLE

Maximum time to

transition to a valid

electrical idle after

sending an EIOS

After sending the required numbers of

EIOSs, the Transmitter must meet all

Electrical Idle specifications within this

time. This is measured from the end of

the last UI of the last EIOS to the

Transmitter in Electrical Idle.

TTX-IDLE-SET-TO

-DIFF-DATA

Maximum time to

transition to valid

differential signaling after

leaving electrical idle

Maximum time to transition to valid

differential signaling after leaving

Electrical Idle. This is considered a

de-bounce time to the Tx.

TCROSSLINK

Crosslink random timeout

This random timeout helps resolve

conflicts in the crosslink configuration.

LTX-SKEW

Lane-to-lane output skew

500 ps

+ 2 UI

500 ps

+ 2 UI

Between any two Lanes within a single

Transmitter.

CTX

AC coupling capacitor

200

All Transmitters must be AC coupled.

The AC coupling is required either within

the media or within the transmitting

component itself.

Table 19: PCIe Differential Transmitter Specifications (Continued)

Symbol

Parameter

2.5 Gbps

5.0 Gbps

Unit

Notes

Min.

Max.

Min.

Max.

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