TSI721 datasheet(13/68 Pages) IDT

13 / 68 page

1. Device Overview > Features

Tsi721 Datasheet

May 5, 2014

Formal Status

This document is confidential and is subject to an NDA.

Integrated Device Technology

• Round-robin scheduling among DMA channels

• DMA descriptors for all channels reside on PCIe side

• Scatter-and-gather with descriptor list

• Supports DMA strides

• Supports up to 64 MB data for a single descriptor

• Supports both read and write descriptors per DMA channel

• Dynamic descriptor chaining

• Flexible addressing modes

— Linear addressing

— Constant addressing

• Descriptor prefetch

• 32 outstanding PCIe requests to root complex

• 64 outstanding S-RIO NREAD/maintenance read requests to S-RIO network

• 64 outstanding S-RIO NWRITE_R/maintenance write requests to S-RIO network

• Supports the following S-RIO transactions:

— NREAD

—NWRITE

—SWRITE

—NWRITE_R

— Maintenance read

— Maintenance write

1.2.6

Miscellaneous Features

•I2C interface supports the following:

— As a slave, being read/written by an external master during normal operations

— As a master, reading external EEPROM during boot load

— As a master, reading/writing other external devices during normal operations

• JTAG 1149.1, 1149.6 (AC JTAG)

• 16 GPIO pins

TSI721 数据表(PDF) 13 Page - Integrated Device Technology

TSI721 数据表(HTML) 13 Page - Integrated Device Technology

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