AC ELECTRICAL CHARACTERISTICS

HOLT INTEGRATED CIRCUITS

13

Figure 17. Switching Waveforms

SI

SO

Hi Impedance

t

P1

MSB

Hi Impedance

CS

SCK

SEL

SU1

t

H1

t

SU2

t

CSR

t

MAX

1/f

HI-8428-R

V

= 3.3V +/- 5%, V

= 12.0V to 16.5V, GND = 0V, T = Operating Temperature Range (unless otherwise specified).

LOGIC

DD

A

PARAMETER

SYM

CONDITION

MIN

TYP

MAX

UNIT

SCK Frequency

f

50% Duty Cycle

0.1

10

MHZ

SCK Pulse Width

t

50

ns

Set-up Time, SCK to

low

t

30

ns

Hold Time,

MAX

W

SU1

CS

CS

CS

CS

CS

CS

CS

CS

CS

CS

low to SCK

t

25

ns

Set-up Time, SENSE valid to

low

t

500

ns

Hold Time,

low to SENSE not valid

t

15

s

Set-up Time, SI to SCK rising

t

25

ns

Hold Time, SCK rising to SI not valid

t

25

ns

Set-up Time, SEL valid to

low

t

30

ns

Hold Time,

high to SEL not valid

t

25

ns

Propagation Delay,

low to SO valid

t

SO loaded with 50pF to Ground

105

ns

Propagation Delay, SCK rising to SO valid

t

SO loaded with 50pF to Ground

90

ns

Propagation Delay,

rising to SO Hi-Z

t

SO loaded with 50pF to Ground

80

ns

recovery time

t

20

ns

Logic Input Capacitance (SCK,

, SI)

C

Guaranteed but not Tested

10

pF

Logic output capacitance (SO Hi-Z)

C

Guaranteed but not Tested

15

pF

H1

SU2

H2

SU3

H3

SU4

H4

P1

P2

P3

CSR

IN

OUT

μ

SENSE

VALID

SU4

t

VALID

VALID

H4

t

W

t

H2

t

SU3

t

H3

t

H1

t

t

P2

t

P3