FUNCTIONAL DESCRIPTION

HOLT INTEGRATED CIRCUITS

4

Configuration Register data is loaded serially from the SPI

as described in the Serial Interface section below. The first

bit of the Configuration Register (CR9) enables built-in-self

test when set to a one. For normal sensing operation, CR9

should be zero. The next eight Configuration Register bits

(CR8-1) set the sensing mode for each sensor. If set to a

one, the sensor is GND/Open, and if programmed to a zero

the sensor is Supply/Open. Data is shifted into the

Configuration Register from the serial interface with bit CR9

first.

GND/OPEN SENSING

For GND/Open sensing, the CRn bit is set to 1. Referring

to the Block Diagram, Figure 1, this selection will connect a

12k

pull-up resistance (including the external 3

through a diode to VDD. This resistance gives extra noise

immunity for detecting the open state while providing

contact wetting current. An open state is first registered

when the SENSE input is greater than 10.5V. The output of

the sensor remains high until a voltage of < 4.5V is

detected at the SENSE input, representing a valid Ground

state, causing the sensor output to go low. The Sensor will

maintain a Ground detect state until the SENSE input

returns to >10.5V. The effect of the two defined thresholds

for Ground and Open introduces 3 - 6V of hysteresis and

provides for a high degree of noise immunity.

Ωk )

Ω

SENSEn

Crn

DRn

Open or > 10.5V

1

(GND/Open)

1

< 4.5V

1

(GND/Open)

0

1 mA

Open or < 7.5V

0 (Supply/Open)

0

> 12V

0 (Supply/Open)

1

Table 1. Function Table

HI-8428-R

OVERVIEW

The HI-8428-R is comprised of 8 sensors, which may be

individually configured for GND/Open or Supply/Open (also

known as 28V/Open) sensing. Eight bits of the on-chip

Configuration Register are used to set the sensor

configuration. A one in the Configuration Register selects

GND/Open and a zero selects Supply/Open mode. A ninth

bit in the Configuration Register is used to enable the chip’s

Built-In-Test (BIT) feature. The logical output from each

sensor is latched into an eight-bit Data Register on the

falling edge of the

input.

Reading from and writing to the Configuration Register and

Data Register is accomplished using a serial interface

compatible with the industry-standard Serial Peripheral

Interface (SPI) bus.

Figure 1 shows a simplified block diagram of the HI-8428-R.

CS

RESET AND INITIALIZATION

CONFIGURATION REGISTER

The HI-8428-R includes an on-chip Power-On Reset (POR)

circuit, which forces the SENSE inputs to a high-impedance

state at power-up. Switches SW1 and SW2 (see Figure 1)

are open. The inputs remain high-impedance until the

Configuration Register is programmed, defining the

GND/Open (SW1 closed / SW2 open), or Supply/Open

(SW1 open / SW2 closed) for each sensor.

The HI-8428-R registers are designed to retain programmed

logic states through VLOGIC power dips down to 1.5V

ensuring reliable operation in noisy environments without

the need to re-initialize the part.

7

654321

First Bit shifted in from SI

8

9

Last Bit shifted in from SI

DATA REGISTER

7

654321

First Bit shifted out of SO

8

Last Bit shifted out of SO

The eight-bit Data Register captures the output state from

the eight discrete sensors. Data is latched on the falling

edge of

. The Data bits are read out from the chip over

the serial interface. Sensor 8 data bit is output first at SO

followed by the remaining seven sensor states. In either

mode (GND/Open or Supply/Open), a logic one is output

when the voltage at the sensor pin input is greater than

the high threshold and a logic zero is output when the

sensor voltage is lower than the low threshold, (see table

1).

Multiple HI-8428-Rs may be daisy-chained together to

allow a single SPI read sequence to program

configuration or capture data from several ICs in one

operation.

CS