© 1996 Microchip Technology Inc.

Preliminary

DS21170A-page 5

24C01SC/02SC

4.0

BUS CHARACTERISTICS

4.1

Slave Address

After generating a START condition, the bus master

transmits the slave address consisting of a 4-bit device

code (1010) for the 24C01SC/02SC, followed by three

don't care bits.

The eighth bit of slave address determines if the master

device wants to read or write to the 24C01SC/02SC

(Figure 4-1).

The 24C01SC/02SC monitors the bus for its corre-

sponding slave address all the time. It generates an

acknowledge bit if the slave address was true, and it is

not in a programming mode.

FIGURE 4-1:

CONTROL BYTE

ALLOCATION

Operation

Control

Code

Chip

Select

R/W

Read

Write

1010

1010

XXX

XXX

1

0

X = Don’t care

R/W

A

10

1

0

X

X

X

READ/WRITE

START

SLAVE ADDRESS

5.0

WRITE OPERATION

5.1

Byte Write

Following the start signal from the master, the device

code (4 bits), the don't care bits (3 bits), and the R/W

bit, which is a logic low, is placed onto the bus by the

master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will follow

after it has generated an acknowledge bit during the

ninth clock cycle. Therefore, the next byte transmitted

by the master is the word address and will be written

into the address pointer of the 24C01SC/02SC. After

receiving

another

acknowledge

signal

from

the

24C01SC/02SC, the master device will transmit the

data word to be written into the addressed memory

location. The 24C01SC/02SC acknowledges again and

the master generates a stop condition. This initiates the

internal

write

cycle,

and

during

this

time

the

24C01SC/02SC will not generate acknowledge signals

(Figure 5-1).

5.2

Page Write

The write control byte, word address, and the first data

byte are transmitted to the 24C01SC/02SC in the same

way as in a byte write. But instead of generating a stop

condition, the master transmits up to eight data bytes to

the 24C01SC/02SC, which are temporarily stored in

the on-chip page buffer and will be written into the

memory after the master has transmitted a stop condi-

tion. After the receipt of each word, the three lower

order address pointer bits are internally incremented by

one. The higher order five bits of the word address

remains constant. If the master should transmit more

than eight words prior to generating the stop condition,

the address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the stop condition is received an inter-

nal write cycle will begin (Figure 5-2).

FIGURE 5-1:

BYTE WRITE

FIGURE 5-2:

PAGE WRITE

S

P

S

T

A

R

T

S

T

O

P

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

A

C

K

A

C

K

A

C

K

CONTROL

BYTE

WORD

ADDRESS

DATA

S

P

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

S

T

A

R

T

S

T

O

P

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n

DATAn + 7

DATAn + 1

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K