© 1996 Microchip Technology Inc.

Preliminary

DS21170A-page 7

24C01SC/02SC

7.4

Noise Protection

circuit which disables the internal erase/write logic if the

The SCL and SDA inputs have Schmitt trigger and filter

circuits which suppress noise spikes to assure proper

device operation even on a noisy bus.

FIGURE 7-1:

CURRENT ADDRESS READ

FIGURE 7-2:

RANDOM READ

FIGURE 7-3:

SEQUENTIAL READ

SP

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

S

T

A

R

T

CONTROL

BYTE

DATA n

A

C

K

N

O

A

C

K

S

T

O

P

S

P

S

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

S

T

A

R

T

S

T

O

P

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n

A

C

K

A

C

K

N

O

A

C

K

CONTROL

BYTE

A

C

K

S

T

A

R

T

P

SDA LINE

BUS ACTIVITY

S

T

O

P

CONTROL

BYTE

DATA n

A

C

K

N

O

A

C

K

A

C

K

A

C

K

A

C

K

DATA n + 1

DATA n + 2

DATA n + X

BUS ACTIVITY

MASTER