24LCS21

DS21127B-page 4

© 1996 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

The

24LCS21

operates

in

two

modes,

the

Transmit-Only Mode and the bi-directional Mode. There

is a separate two wire protocol to support each mode,

each having a separate clock input but sharing a com-

mon data line (SDA). The device enters the Trans-

mit-Only Mode upon power-up. In this mode, the device

transmits data bits on the SDA pin in response to a

clock signal on the VCLK pin. The device will remain in

this mode until a valid high to low transition is placed on

the SCL input. When a valid transition on SCL is recog-

nized, the device will switch into the bi-directional

Mode. The only way to switch the device back to the

Transmit-Only Mode is to remove power from the

device.

2.1

Transmit-Only Mode

The device will power up in the Transmit-Only Mode at

address 00H. This mode supports a unidirectional two

wire protocol for continuous transmission of the

contents of the memory array. This device requires that

it be initialized prior to valid data being sent in the Trans-

mit-Only Mode (see Initialization Procedure, below). In

this mode, data is transmitted on the SDA pin in 8-bit

bytes, with each byte followed by a ninth, null bit

(Figure 2-1). The clock source for the Transmit-Only

Mode is provided on the VCLK pin, and a data bit is out-

put on the rising edge on this pin. The eight bits in each

byte are transmitted most significant bit first. Each byte

within the memory array will be output in sequence.

When the last byte in the memory array is transmitted,

the internal address pointers will wrap around to the

first memory location (00H) and continue. The bi-direc-

tional Mode Clock (SCL) pin must be held high for the

device to remain in the Transmit-Only Mode.

2.2

Initialization Procedure

Transmit-Only Mode. Nine clock cycles on the VCLK pin

must be given to the device for it to perform internal

sychronization. During this period, the SDA pin will be

in a high impedance state. On the rising edge of the

tenth clock cycle, the device will output the first valid

data bit which will be the most significant bit in address

00h. (Figure 2-2).

FIGURE 2-1: TRANSMIT ONLY MODE

FIGURE 2-2: DEVICE INITIALIZATION

SCL

SDA

VCLK

Bit 1 (LSB)

Null Bit

Bit 1 (MSB)

Bit 7

Bit 8

Bit 7

High Impedance for 9 clock cycles

12

89

10

11

SCL

SDA

VCLK

Vcc