24LCS21

DS21127B-page 8

© 1996 Microchip Technology Inc.

4.2

Page Write

The write control byte, word address and the first data

byte are transmitted to the 24LCS21 in the same way

as in a byte write. But instead of generating a stop

condition the master transmits up to eight data bytes to

the 24LCS21 which are temporarily stored in the

on-chip page buffer and will be written into the memory

after the master has transmitted a stop condition. After

the receipt of each word, the three lower order address

pointer bits are internally incremented by one. The

higher order five bits of the word address remains

constant. If the master should transmit more than eight

words prior to generating the stop condition, the

address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the stop condition is received an

internal write cycle will begin (Figure 5-2).

It is required that VCLK be held at a logic high level

during command and data transfer in order to program

the device. This applies to both byte write and page

write operation. Note, however, that the VCLK is

ignored during the self-timed program operation.

Changing VCLK from high to low during the self-timed

program operation will not halt programming of the

device.

5.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write

command has been issued from the master, the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

sending a start condition followed by the control byte for

a write command (R/W = 0). If the device is still busy

with the write cycle, then no ACK will be returned. If the

cycle is complete, then the device will return the ACK

and the master can then proceed with the next read or

write command. See Figure 5-1 for the flow diagram.

FIGURE 5-1: ACKNOWLEDGE POLLING

FLOW

Did Device

Acknowledge

(ACK = 0)?

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Next

Operation

No

Yes

FIGURE 5-2: PAGE WRITE

BUS

MASTER

SDA LINE

BUS

CONTROL

BYTE

WORD

ADDRESS (1)

S

T

O

P

S

T

A

R

T

A

C

K

A

C

K

A

C

K

ACTIVITY:

ACTIVITY:

A

C

K

A

C

K

DATA n + 1

DATA n + 7

DATA (n)

P

S

VCLK