© 1996 Microchip Technology Inc.

DS21127B-page 7

24LCS21

3.1.6

SLAVE ADDRESS

After generating a START condition, the bus master

transmits the slave address consisting of a 7-bit device

code (1010000) for the 24LCS21.

The eighth bit of slave address determines whether the

master device wants to read or write to the 24LCS21

(Figure 3-5).

The 24LCS21 monitors the bus for its corresponding

slave

address

continuously.

It

generates

an

acknowledge bit if the slave address was true and it is

not in a programming mode.

FIGURE 3-5: CONTROL BYTE ALLOCATION

Operation

Slave Address

R/W

Read

1010000

1

Write

1010000

0

SLAVE ADDRESS

101

00

0

0

R/W

A

START

READ/WRITE

4.0

WRITE OPERATION

4.1

Byte Write

Following the start signal from the master, the slave

address (4 bits), three zero bits (000) and the R/W bit

which is a logic low are placed onto the bus by the

master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will follow

after it has generated an acknowledge bit during the

ninth clock cycle. Therefore, the next byte transmitted

by the master is the word address and will be written

into the address pointer of the 24LCS21. After receiving

another acknowledge signal from the 24LCS21 the

master device will transmit the data word to be written

into the addressed memory location. The 24LCS21

acknowledges again and the master generates a stop

condition. This initiates the internal write cycle, and dur-

ing this time the 24LCS21 will not generate acknowl-

edge signals (Figure 4-1).

It is required that VCLK be held at a logic high level

during command and data transfer in order to program

the device. This applies to both byte write and page

write operation. Note, however, that the VCLK is

ignored during the self-timed program operation.

Changing VCLK from high to low during the self-timed

program operation will not halt programming of the

device.

FIGURE 4-1: BYTE WRITE

FIGURE 4-2: VCLK WRITE ENABLE TIMING

BUS ACTIVITY:

MASTER

SDA LINE

BUS ACTIVITY:

CONTROL

BYTE

WORD

ADDRESS

DATA

S

T

O

P

S

T

A

R

T

A

C

K

S

P

A

C

K

A

C

K

VCLK

VCLK

SDA

IN

SCL