© 1999 Microchip Technology Inc.

Preliminary

DS21298B-page 3

MCP3204/3208

Analog Inputs (Continued)

Switch Resistance

1K

Ω

See Figure 4-1

Sample Capacitor

20

pF

See Figure 4-1

Digital Input/Output

Data Coding Format

Straight Binary

High Level Input Voltage

V

IH

0.7 V

DD

V

Low Level Input Voltage

V

IL

0.3 V

DD

V

High Level Output Voltage

V

OH

4.1

V

I

Low Level Output Voltage

V

OL

0.4

V

I

Input Leakage Current

I

LI

-10

10

µA

V

Output Leakage Current

I

LO

-10

10

µA

V

Pin Capacitance

(All Inputs/Outputs)

C

10

pF

V

T

Timing Parameters

Clock Frequency

f

CLK

2.0

1.0

MHz

MHz

V

V

Clock High Time

t

HI

250

ns

Clock Low Time

t

LO

250

ns

CS Fall To First Rising CLK

Edge

t

SUCS

100

ns

Data Input Setup Time

t

SU

50

ns

Data Input Hold Time

t

HD

50

ns

CLK Fall To Output Data Valid

t

DO

200

ns

See Test Circuits, Figure 1-2

CLK Fall To Output Enable

t

EN

200

ns

See Test Circuits, Figure 1-2

CS Rise To Output Disable

t

DIS

100

ns

See Test Circuits, Figure 1-2

CS Disable Time

t

CSH

500

ns

D

t

R

100

ns

See Test Circuits, Figure 1-2

(Note 1)

D

t

F

100

ns

See Test Circuits, Figure 1-2

(Note 1)

Power Requirements

Operating Voltage

V

DD

2.7

5.5

V

Operating Current

I

DD

320

225

400

µA

V

V

Standby Current

I

DDS

0.5

2

µA

CS = V

Note 1: This parameter is guaranteed by characterization and not 100% tested.

Note 2: See graphs that relate linearity performance to V

Note 3: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity

performance, especially at elevated temperatures. See Section 6.2 for more information.

ELECTRICAL CHARACTERISTICS (CONTINUED)

All parameters apply at V

f

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNITS

CONDITIONS