MCP3204/3208

DS21298B-page 16

Preliminary

© 1999 Microchip Technology Inc.

6.0

APPLICATIONS INFORMATION

6.1

Using the MCP3204/3208 with

Microcontroller (MCU) SPI Ports

With most microcontroller SPI ports, it is required to

send groups of eight bits. It is also required that the

microcontroller SPI port be configured to clock out data

on the falling edge of clock and latch data in on the rising

edge. Because communication with the MCP3204/3208

devices may not need multiples of eight clocks, it will be

necessary to provide more clocks than are required.

This is usually done by sending ‘leading zeros’ before

the start bit. As an example, Figure 6-1 and Figure 6-2

shows how the MCP3204/3208 can be interfaced to a

MCU with a hardware SPI port. Figure 6-1 depicts the

operation shown in SPI Mode 0,0 which requires that the

SCLK from the MCU idles in the ‘low’ state, while

Figure 6-2 shows the similar case of SPI Mode 1,1

where the clock idles in the ‘high’ state.

As shown in Figure 6-1, the first byte transmitted to the

A/D Converter contains five leading zeros before the

start bit. Arranging the leading zeros this way produces

the output 12 bits to fall in positions easily manipulated

by the MCU. The MSB is clocked out of the A/D Con-

verter on the falling edge of clock number 12. After the

second eight clocks have been sent to the device, the

MCUs receive buffer will contain three unknown bits

(the output is at high impedance for the first two clocks),

the null bit and the highest order four bits of the conver-

sion. After the third byte has been sent to the device, the

receive register will contain the lowest order eight bits of

the conversion results. Easier manipulation of the con-

verted data can be obtained by using this method.

Figure 6-2 shows the same thing in SPI Mode 1,1

which requires that the clock idles in the high state. As

with mode 0,0, the A/D Converter outputs data on the

falling edge of the clock and the MCU latches data from

the A/D Converter in on the rising edge of the clock.

FIGURE 6-1:

SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).

FIGURE 6-2:

SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).

1

2

3

4

5

6

7

8

9

10

1112

1314

15

16

CS

SCLK

X = Don’t Care Bits

17

18

19

20

21

22

23

24

NULL

BIT

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

HI-Z

MCU latches data from A/D Converter

Data is clocked out of

A/D Converter on falling edges

on rising edges of SCLK

DO

Don’t Care

SGL/

DIFF

D1

D2

Start

000

00

1

XX

X

X

X

DO

XXX

X

X

XX

X

B7

B6

B5

B4

B3

B2

B1

B0

B11

B10

B9

B8

0

??

????

??

???

D1

D2

SGL/

DIFF

Start

Bit

(Null)

MCU Transmitted Data

(Aligned with falling

edge of clock)

MCU Received Data

(Aligned with rising

edge of clock)

X

Data stored into MCU receive register

after transmission of first 8 bits

Data stored into MCU receive register

after transmission of second 8 bits

Data stored into MCU receive register

after transmission of last 8 bits

1

2

3

4

5

6

7

8

9

10

1112

1314

15

16

CS

SCLK

X = Don’t Care Bits

17

18

19

20

21

22

23

24

DO

Don’t Care

NULL

BIT

B11

B10

B9

B8

B6

B5

B4

B3

B2

B1

B0

HI-Z

000

0

0

1

XX

X

X

X

DO

SGL/

DIFF

XXX

X

X

XX

X

B7

B6

B5

B4

B3

B2

B1

B0

B11

B10

B9

B8

0

????

????

??

?

MCU latches data from A/D Converter

on rising edges of SCLK

Data is clocked out of

A/D Converter on falling edges

D1

D2

SGL/

DIFF

Start

Bit

(Null)

D1

D2

Start

MCU Transmitted Data

(Aligned with falling

edge of clock)

MCU Received Data

(Aligned with rising

edge of clock)

B7

X

Data stored into MCU receive register

after transmission of first 8 bits

Data stored into MCU receive register

after transmission of second 8 bits

Data stored into MCU receive register

after transmission of last 8 bits