PIC16C925SLASHCL datasheet(43/182 Pages) MICROCHIP

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 2001 Microchip Technology Inc.

Preliminary

DS39544A-page 41

PIC16C925/926

5.0

TIMER0 MODULE

The Timer0 module has the following features:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt-on-overflow from FFh to 00h

• Edge select for external clock

Figure 5-1 is a simplified block diagram of the Timer0

module.

Timer mode is selected by clearing bit T0CS

(OPTION<5>). In Timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

the TMR0 register is written, the increment is inhibited

for the following two instruction cycles (Figure 5-2 and

Figure 5-3). The user can work around this by writing

an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS

(OPTION<5>). In Counter mode, Timer0 will increment

either on every rising, or falling edge of pin RA4/T0CKI.

The incrementing edge is determined by the Timer0

Source Edge Select bit T0SE (OPTION<4>). Clearing

bit T0SE selects the rising edge. Restrictions on the

external clock input are discussed in detail in

Section 5.2.

The prescaler is mutually exclusively shared between

the Timer0 module and the Watchdog Timer. The

prescaler assignment is controlled in software by con-

trol bit PSA (OPTION<3>). Clearing bit PSA will assign

the prescaler to the Timer0 module. The prescaler is

not readable or writable. When the prescaler is

assigned to the Timer0 module, prescale values of 1:2,

1:4,..., 1:256 are selectable. Section 5.3 details the

operation of the prescaler.

5.1

Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister overflows from FFh to 00h. This overflow sets bit

TMR0IF (INTCON<2>). The interrupt can be masked

by clearing bit T0IE (INTCON<5>). Bit TMR0IF must be

cleared in software by the Timer0 module Interrupt Ser-

vice Routine before re-enabling this interrupt. The

TMR0 interrupt cannot awaken the processor from

SLEEP, since the timer is shut-off during SLEEP.

Figure 5-4 displays the Timer0 interrupt timing.

FIGURE 5-1:

TIMER0 BLOCK DIAGRAM

Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).

2: The prescaler is shared with the Watchdog Timer (refer to Figure 5-6 for detailed block diagram).

RA4/T0CKI

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

Clocks

TMR0

PSout

(2 cycle delay)

PSout

Data Bus

PSA

PS2, PS1, PS0

Set Interrupt

Flag bit TMR0IF

on Overflow

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