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PIC16C925/CL 数据表(PDF) 78 Page - Microchip Technology |
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PIC16C925/CL 数据表(HTML) 78 Page - Microchip Technology |
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78 / 182 page  PIC16C925/926 DS39544A-page 76 Preliminary 2001 Microchip Technology Inc. REGISTER 10-2: ADCON1 REGISTER (ADDRESS 9Fh) The ADRESH:ADRESL registers contain the 10-bit result of the A/D conversion. When the A/D conversion is complete, the result is loaded into this A/D result reg- ister pair, the GO/DONE bit (ADCON0<2>) is cleared and the A/D interrupt flag bit ADIF is set. The block dia- gram of the A/D module is shown in Figure 10-1. After the A/D module has been configured as desired, the selected channel must be acquired before the con- version is started. The analog input channels must have their corresponding TRIS bits selected as inputs. To determine sample time, see Section 10.1. After this acquisition time has elapsed, the A/D conversion can be started. U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. 6 Most Significant bits of ADRESH are read as ‘0’. 0 = Left justified. 6 Least Significant bits of ADRESL are read as ‘0’. bit 6-4 Unimplemented: Read as '0' bit 3-0 PCFG<3:0>: A/D Port Configuration Control bits: Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown A = Analog input D = Digital I/O Note 1: This column indicates the number of analog channels available as A/D inputs and the number of analog channels used as voltage reference inputs. PCFG<3:0> AN4 RA5 AN3 RA3 AN2 RA2 AN1 RA1 AN0 RA0 VREF+VREF- CHAN/ Refs(1) 0000 A A AAA VDD VSS 5/0 0001 AVREF+ AAA RA3 VSS 4/1 0010 A A AAA VDD VSS 5/0 0011 AVREF+ AAA RA3 VSS 4/1 0100 DA D A A VDD VSS 3/0 0101 DVREF+D A A RA3 VSS 2/1 011x D D DDD VDD VSS 0/0 1000 AVREF+VREF-A A RA3 RA2 3/2 1001 A A AAA VDD VSS 5/0 1010 AVREF+ AAA RA3 VSS 4/1 1011 AVREF+VREF-A A RA3 RA2 3/2 1100 AVREF+VREF-A A RA3 RA2 3/2 1101 DVREF+VREF-A A RA3 RA2 2/2 1110 DD D D A VDD VSS 1/0 1111 DVREF+VREF-D A RA3 RA2 1/2 |
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