PIC16C925SLASHCL datasheet(103/182 Pages) MICROCHIP

103 / 182 page

 2001 Microchip Technology Inc.

Preliminary

DS39544A-page 101

PIC16C925/926

12.3

RESET

The PIC16C9XX differentiates between various kinds

of RESET:

• Power-on Reset (POR)

• MCLR Reset during normal operation

• MCLR Reset during SLEEP

• WDT Reset (normal operation)

• Brown-out Reset (BOR)

Some registers are not affected in any RESET condi-

tion; their status is unknown on POR and unchanged in

any other RESET. Most other registers are reset to a

“RESET state” on Power-on Reset (POR), on the

MCLR and WDT Reset, and on MCLR Reset during

SLEEP. They are not affected by a WDT Wake-up,

which is viewed as the resumption of normal operation.

The TO and PD bits are set or cleared differently in dif-

ferent RESET situations, as indicated in Table 12-4.

These bits are used in software to determine the nature

of the RESET. See Table 12-6 for a full description of

RESET states of all registers.

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 12-6.

The devices all have a MCLR noise filter in the MCLR

Reset path. The filter will detect and ignore small

pulses.

It should be noted that a WDT Reset does not drive

MCLR pin low.

FIGURE 12-6:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR

VDD

OSC1

WDT

Module

VDD Rise

Detect

OST/PWRT

On-chip

RC OSC

WDT

Time-out

Power-on

OST

10-bit Ripple Counter

PWRT

Chip_Reset

10-bit Ripple Counter

Reset

Enable OST(2)

Enable PWRT(2)

SLEEP

Note 1:

This is a separate oscillator from the RC oscillator of the CLKIN pin.

See Table 12-3 for various time-out situations.

Brown-out

Reset

BOREN

(1)

Reset

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