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ML6461CS 数据表(PDF) 24 Page - Micro Linear Corporation |
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ML6461CS 数据表(HTML) 24 Page - Micro Linear Corporation |
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24 / 30 page ![]() ML6461 24 MODE PRESET1 PRESET0 CC CNTR A 0 0 XX XXXXXXXX B 0 1 XX 09080209 C 1 0 XX 1C080209 D 1 1 XX 11080209 X = don't care Mode Description Mode A: All register contents are programmed through serial interface. Mode B: Master mode, CCIR656 rate, analog blanking. Mode C: Slave mode, SAV and EAV codes, CCIR656 rate, digital blanking. Mode D: Slave mode, external sync at start of line, Square pixel rate, analog blanking Table 8. Preset Modes and Register Values PRESET PIN CONTROL The ML6461 can be controlled by a pair of preset mode pins. These pins do not allow access to all of the programmable features of the ML6461, but are intended to provide a simpler interface for most applications. Refer to Table 8 for preset modes. SERIAL BUS OPERATION The serial bus control in the ML6461 has two levels of addressing: Device Addressing and Functional Addressing. Device Addressing: Figures 15, 16, and 17 show the physical waveforms generated in order to address the ML6461. There are six basic parts of the waveform: 1. Start Indication: Clock Cycle 0 2. Device Address Shifted in: Clock Cycle 1 through 8 3. Device Address Strobed and Decoded: Clock Cycle 9 4. Function Address Shifted in: Clock Cycle 10 through 17 5. Function Address Strobed and Decoded: Clock Cycle 18 6. Data Shifted in 8 bits at a time, MSB first: Clock Cycle 19 through 26 7. Data Shifted: Clock Cycle 27 8. Repeat strep 6 & 7 until all data is clocked in. 9. Stop indication: After Last Clock Cycle (54 for CC, 54 for CNTR) Note: data at SDATA is ignored at steps 3, 5, and 7. Device & Function Addressing: Figures 15, 16, an17 show the register address procedure of the ML6461. FUNCTIONAL DESCRIPTION (Continued) Device Address (8 bit) 1011 0100 (Hex = B4) Function Address (8 bit) Closed Caption Data Registers (CC): 0000 0000 (Hex = 00) Control Registers (CNTR): 0000 0011 (Hex = 03) Number of Data Bits Closed Caption Data Registers (CC): 4 x 8 bits Control Registers (CNTR): 4 x 8 bits CONTROL REGISTER DEFAULT SETTINGS At Power up, the ML6461 default settings are as follows: • Control Register is undefined when the serial bus mode is enabled. • Chip is ready to process video • Preset Pins are available and if used will configure the control register. • Must write logic “0” (zero) to A30 to get video To get black at power up will require logic “1” in A30. |
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