REV. 0

ADP3164

–6–

THEORY OF OPERATION

The ADP3164 combines a current-mode, fixed frequency PWM

controller with multiphase logic outputs for use in a 4-phase syn-

chronous buck power converter. Multiphase operation is important

for switching the high currents required by high performance

microprocessors. Handling the high current in a single-phase

converter would place unreasonable requirements on the power

components such as inductor wire size and MOSFET ON-

resistance and thermal dissipation. The ADP3164’s high side

current sensing topology ensures that the load currents are bal-

anced in each phase, such that no single phase has to carry

more than it’s share of the power. An additional benefit of high

side current sensing over output current sensing is that the

average current through the sense resistor is reduced by the duty

cycle of the converter allowing the use of a lower power, lower

cost resistor. The outputs of the ADP3164 are logic drivers only

and are not intended to directly drive external power MOSFETs.

Instead, the ADP3164 should be paired with drivers such as

the ADP3413.

Table I. Output Voltage vs. VID Code

VID4

VID3

VID2

VID1

VID0

11111No CPU

111101.100 V

111011.125 V

111001.150 V

110111.175 V

110101.200 V

110011.225 V

110001.250 V

101111.275 V

101101.300 V

101011.325 V

101001.350 V

100111.375 V

100101.400 V

100011.425 V

100001.450 V

011111.475 V

011101.500 V

011011.525 V

011001.550 V

010111.575 V

010101.600 V

010011.625 V

010001.650 V

001111.675 V

001101.700 V

001011.725 V

001001.750 V

000111.775 V

000101.800 V

000011.825 V

000001.850 V

The frequency of the ADP3164 is set by an external capacitor

connected to the CT pin. The error amplifier and current sense

comparator control the duty cycle of the PWM outputs to main-

tain regulation. The maximum duty cycle per phase is inherently

limited to 25%. While one phase is on, all other phases remain

off. In no case can more than one output be high at any time.

Output Voltage Sensing

The output voltage is sensed at the FB pin allowing for remote

sensing. To maintain the accuracy of the remote sensing, the

GND pin should also be connected close to the load. A voltage

voltage and a programmable reference voltage. The reference

voltage is programmed between 1.1 V and 1.85 V by an internal

5-bit DAC, which reads the code at the voltage identification

(VID) pins. (Refer to Table I for the output voltage versus VID

pin code information.)

Active Voltage Positioning

The ADP3164 uses Analog Devices Optimal Positioning Tech-

nology (ADOPT), a unique supplemental regulation technique

that uses active voltage positioning and provides optimal com-

pensation for load transients. When implemented, ADOPT adjusts

the output voltage as a function of the load current, so that it is

always optimally positioned for a load transient. Standard (passive)

voltage positioning has poor dynamic performance, rendering it

ineffective under the stringent repetitive transient conditions

required by high performance processors. ADOPT, however,

provides a bandwidth for transient response that is limited only

by parasitic output inductance. This yields optimal load tran-

sient response with the minimum number of output capacitors.

Reference Output

A 3.0 V reference is available on the ADP3164. This reference

is normally used to accurately set the voltage positioning using a

resistor divider to the COMP pin. In addition, the reference can

be used for other functions such as generating a regulated voltage

with an external amplifier. The reference is bypassed with a 1 nF

capacitor to ground. It is not intended to drive larger capacitive

loads, and it should not be used to provide more than 300 A of

output current.

Cycle-by-Cycle Operation

During normal operation (when the output voltage is regulated),

the voltage-error amplifier and the current comparator are the

main control elements. The free running oscillator ramps between

0 V and 3 V. When the voltage on the CT pin reaches 3 V, the

oscillator sets the driver logic, which sets PWM1 high. During

the ON time of Phase 1, the driver IC turns on the Phase 1 high

side MOSFET. The CS+ and CS– pins monitor the current

through the sense resistor that feeds all of the high side MOSFETs.

When the voltage between the two pins exceeds the threshold

level, the driver logic is reset and the PWM1 output goes low.

This signals the driver IC to turn off the Phase 1 high side

MOSFET and turn on the Phase 1 low side MOSFET. On the

next cycle of the oscillator, the driver logic toggles and sets

PWM2 high. The current is then steered through the second

phase. This cycle continues for each of the PWM outputs.

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