ASM1232LPF datasheet(5/12 Pages) ONSEMI

5 / 12 page

ASM1232LP, ASM1232LPS

http://onsemi.com

Detailed Description

The ASM1232LP/LPS monitors the microprocessor or

micro controller power supply and generates reset signal,

both active HIGH and Active LOW, that halt processor

operation whenever the power supply voltage levels are

outside a predetermined tolerance.

RESET and RESET outputs

RESET is an active HIGH signal developed by a CMOS

push−pull output stage and is the logical opposite to RESET.

RESET is an active LOW signal. It is developed with an

open drain driver. A pull up resistor of typical value 10 k

to 50 k

W is required to connect with the output.

Trip Point Tolerance Selection

The TOL input is used to determine the level VCC can vary

below 5 V without asserting a reset. With TOL connected to

VCC, RESET and RESET become active whenever VCC

falls below 4.5 V. RESET and RESET become active when

the VCC falls below 4.75 V if TOL is connected to ground.

After VCC has risen above the trip point set by TOL,

RESET and RESET remain active for a minimum time

period of 250 ms. On power−down, once VCC falls below the

reset threshold RESET stays LOW and is guaranteed to be

0.4 V or less until VCC drops below 1.2 V. The active HIGH

reset signal is valid down to a VCC level of 1.2 V also.

Tolerance Select

Tolerance

TRIP Point Voltage (V)

Min

Nom

Max

TOL = VCC

10%

4.25

4.37

4.49

TOL = GND

4.5

4.62

4.74

Figure 3. Timing Diagram: Power Up

Figure 4. Timing Diagram: Power Down

ASM1232LPF 数据表(PDF) 5 Page - ON Semiconductor

ASM1232LPF 数据表(HTML) 5 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

数据表下载