ASM1232LP, ASM1232LPS

http://onsemi.com

7

Watchdog Timer and ST Input

A watchdog timer stops and restarts a microprocessor that

is “hung−up”. The

mP must toggle the ST input within a set

period (as selectable through TD input) to verify proper

software execution. If the ST is not toggled low within the

minimum timeout period, reset signals become active. In

power−up after the supply voltage returns to an in−tolerance

condition, the reset signal remains active for 250 ms

minimum, allowing the power supply and system

microprocessor to stabilize. ST pulses as short as 20 ns can

be detected.

Figure 7. Timing Diagram: Strobe Input

Timeouts periods of approximately 150 ms, 610 ms or 1,200 ms are selected through the TD pin.

TD Voltage level

Watchdog Time−out Period (ms)

Min

Nom

Max

GND

62.5

150

250

Floating

250

610

1000

500

1200

2000

The watchdog timer cannot be disabled. It must be strobed with a high−to−low transition to avoid watchdog timeout and reset.

Figure 8. Application Circuit: Watchdog Timer