CS5307GDWR24 datasheet(14/24 Pages) ONSEMI

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CS5307

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Due to the faster than ideal RC time constant, there is an

overshoot of 50% and the overshoot decays with a 200 μs

time constant. With this compensation, the OCSET pin

threshold must be set more than 50% above the full load

current to avoid triggering current limit during a large output

load step.

Transient Response and Adaptive Voltage Positioning

For applications with fast transient currents, the output

filter is frequently sized larger than ripple currents require in

order to reduce voltage excursions during load transients.

Adaptive voltage positioning can reduce peak−peak output

voltage deviations during load transients and allow for a

smaller output filter. The output voltage can be set higher

than nominal at light loads to reduce output voltage sag

when the load current is applied. Similarly, the output

voltage can be set lower than nominal during heavy loads to

reduce overshoot when the load current is removed. For low

current applications, a droop resistor can provide fast,

accurate adaptive positioning. However, at high currents,

the loss in a droop resistor becomes excessive. For example,

a 50 A converter with a 1 mΩ resistor would provide a 50

mV change in output voltage between no load and full load

and would dissipate 2.5 W.

Lossless adaptive voltage positioning (AVP) is an

alternative to using a droop resistor, but it must respond to

changes in load current. Figure 18 shows how AVP works.

The waveform labeled “normal” shows a converter without

AVP. On the left, the output voltage sags when the output

current is stepped up and later overshoots when current is

stepped back down. With fast (ideal) AVP, the peak−to−peak

excursions are cut in half. In the slow AVP waveform, the

output voltage is not repositioned quickly enough after

current is stepped up and the upper limit is exceeded.

The controller can be configured to adjust the output

voltage based on the output current of the converter. (Refer

to the application diagram in Figure 1). To set the no−load

positioning, a resistor is placed between the output voltage

and VFB pin. The VFB bias current will develop a voltage

across the resistor to adjust the no−load output voltage. The

VFB bias current is dependent on the value of ROSC as shown

in the datasheets.

During no−load conditions, the VDRP pin is at the same

voltage as the VFB pin, so none of the VFB bias current flows

through the VDRP resistor. When output current increases,

the VDRP pin voltage increases proportionally. Current set

by the VDRP resistor offsets the VFB bias current, causing the

output voltage to decrease.

The response during the first few microseconds of a load

transient is controlled primarily by power stage output

impedance, and by the ESR and ESL of the output filter. The

transition between fast and slow positioning is controlled by

the total ramp size and the error amp compensation. If the

ramp size is too large or the error amp too slow, there will be

a long transition to the final voltage after a transient. This

will be most apparent with low capacitance output filters.

Figure 17. Inductive Sensing Waveform During a

Load Step with Fast RC Time Constant (50 μs/div)

Adaptive Positioning

Normal

Fast

Slow

Limits

Figure 18. Adaptive Voltage Positioning

Overvoltage Protection

Overvoltage protection (OVP) is provided as a result of

the normal operation of the Enhanced V2 control topology

with synchronous rectifiers. The control loop responds to an

overvoltage condition within 40 ns, causing the GATEx

output to shut off. The (external) MOSFET driver should

react normally to turn off the top MOSFET and turn on the

bottom MOSFET. This results in a “crowbar” action to

clamp the output voltage and prevent damage to the load.

The regulator will remain in this state until the overvoltage

condition ends or the input voltage is pulled low.

Power Good

According to the latest specifications, the Power Good

(PWRGD) signal must be asserted when the output voltage

is within a window defined by the VID code, as shown in

Figure 19.

The PWRGDS pin is provided to allow the PWRGD

comparators to accurately sense the output voltage. The

effect of the PWRGD lower threshold can be modified using

a resistor divider from the output to PWRGDS to ground, as

shown in Figure 20.

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