CS5307GDWR24 datasheet(20/24 Pages) ONSEMI

20 / 24 page

CS5307

http://onsemi.com

Vfdiode is the forward voltage of the MOSFET’s intrinsic

diode at the converter output current.

t_nonoverlap is the non−overlap time between the upper

and lower gate drivers to prevent cross conduction.

This time is usually specified in the data sheet for the

control IC.

When the MOSFET power dissipations are known, the

designer can calculate the required thermal impedance to

maintain a specified junction temperature at the worst case

ambient operating temperature.

qT t (TJ * TA) PD

(28)

where:

θT is the total thermal impedance (θJC + θSA);

θJC is the junction−to−case thermal impedance of the

MOSFET;

θSA is the sink−to−ambient thermal impedance of the

heatsink assuming direct mounting of the MOSFET (no

thermal “pad” is used);

TJ is the specified maximum allowed junction

temperature;

TA is the worst case ambient operating temperature.

For TO−220 and TO−263 packages, standard FR−4

copper clad circuit boards will have approximate thermal

resistances (θSA) as shown below:

Pad Size

(in2/mm2)

Single−Sided

1 oz. Copper

0.50/323

60−65°C/W

0.75/484

55−60°C/W

1.00/645

50−55°C/W

1.50/968

45−50°C/W

As with any power design, proper laboratory testing

should be performed to insure the design will dissipate the

required power under worst case operating conditions.

Variables considered during testing should include

maximum ambient temperature, minimum airflow,

maximum input voltage, maximum loading and component

variations (i.e., worst case MOSFET RDS(on)). Also, the

inductors and capacitors share the MOSFET’s heatsinks and

will add heat and raise the temperature of the circuit board

and MOSFET. For any new design, it is advisable to have as

much heatsink area as possible. All too often, new designs are

found to be too hot and require re−design to add heatsinking.

6. Adaptive Voltage Positioning

There are two resistors that determine the Adaptive

Voltage Positioning: RFB and RDRP. RFB establishes the

no−load “high” voltage position and RDRP determines the

full−load “droop” voltage.

Resistor RFB is connected between VCORE and the VFB

pin of the controller. At no load, this resistor will conduct the

internal bias current of the VFB pin and develop a voltage

drop from VCORE to the VFB pin. Because the error amplifier

regulates VFB to the DAC setting, the output voltage,

VCORE, will be lower by the amount IBIASVFB ⋅ RFB. This

condition is shown in Figure 24.

To calculate RFB, the designer must specify the no−load

voltage decrease below the VID setting (ΔVNO−LOAD) and

determine the VFB bias current. Usually, the no−load voltage

increase is specified in the design guide for the processor

that is available from the manufacturer. The VFB bias current

is determined by the value of the resistor from ROSC to

ground (see Figure 4 in the data sheet for a graph of

IBIASVFB versus ROSC). The value of RFB can then be

calculated:

RFB + DVNO−LOAD IBIASVFB

(29)

−

RCS1

CS1

CCS1

0 A

GVDRP

−

RCSx

CSx

CCSx

0 A

GVDRP

CSREF

COMP

Error

Amp

VID Setting

IBIASVFB

RDRP

RFB

VDRP = VID

VFB = VID

VCORE

IDRP = 0

IFB = IBIASVFB

VCORE = VID + IBIASVFB w RFB

Figure 24. AVP Circuitry at No−Load

+ −

CS5307GDWR24 数据表(PDF) 20 Page - ON Semiconductor

CS5307GDWR24 数据表(HTML) 20 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

数据表下载