SM5846AP

NIPPON PRECISION CIRCUITS—36

NC9616BE

1998.01

NIPPON PRECISION CIRCUITS INC.

NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to

improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for

the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits

are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision

Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.

The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or

malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,

including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or

indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.

NIPPON PRECISION CIRCUITS INC.

4-3, Fukuzumi 2 chome

Koto-ku, Tokyo 135-8430, Japan

Telephone: 03-3642-6661

Facsimile: 03-3642-6698

Audio

ICs

Internal control flag/D-ATT attenuator

register initial values

When external muting is required

The SM5846AP has a relatively long group delay

time because multi-stage filters are employed to

achieve the desired filter characteristics. Under the

following conditions, undesirable noise output can

occur during the group delay time period. In this

case, it may be necessary to use external muting.

s

When power is first applied.

The state of internal registers may be undefined

during power-ON.

s

When switching the operating mode.

When switching the operating mode using HS,

ASEL1 and ASEL2, the internal register assign-

ments may be changed.

s

If the LRCI and/or XTI clock stop.

If a disturbance occurs during an input data cycle,

normal filter output may not be achieved.

s

When switching deemphasis ON/OFF.

Switching the deemphasis filter parameters may

cause switching noise output.

s

When switching the sampling frequency (clock

frequency).

s

When switching between input/output data for-

mats (including LRCI clock polarity switching).

Note that switching MDS is inhibited during system

operation.

Test Precautions

The following conditions should be maintained for

normal operation.

s

MDS and DITH inputs should not be simulta-

neously LOW.

s

TEST1 (bit 4 of mode flag 1 register) should not

be set to 1.

s

TEST2 (bit 4 of mode flag 3 register) should be set

to 0 after system reset (including power-ON).

s

Mode flag 3 register bit 5 and/or bit 7 should not

be set to 0.

Register

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

D-ATT attenuation

0

a1 = 0

a2 = 0

a3 = 0

a4 = 0

a5 = 0

a6 = 0

a7 = 0

Mode flag 1

1

0

SYNC = 1

TEST1 = 0

HS = 1

FSEL1 = 1

FSEL2 = 1

DEEM = 0

Mode flag 2

1

1

MUTE = 1

DITH = 1

OBS = 0

IBS1 = 1

IBS2 = 0

1

Mode flag 3

1

1

ASEL1 = 1

ASEL2 = 1

1

TEST2 = 1

1

0