OSC

PWM

LPF

DCL

OUT

IN

0

1 S

Isolation Barrier

Low ± Frequency

Channel

(DC...100 kbps)

High ± Frequency

Channel

(100 kbps ...25 Mbps )

Polarity and

Threshold Selection

Polarity and Threshold Selection

ISO7330C, ISO7330FC, ISO7331C, ISO7331FC

SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015

www.ti.com

8 Detailed Description

8.1 Overview

The isolator in Figure 15 is based on a capacitive isolation barrier technique. The I/O channel of the device

consists of two internal data channels, a high-frequency (HF) channel with a bandwidth from 100 kbps up to 25

Mbps, and a low-frequency (LF) channel covering the range from 100 kbps down to DC.

In principle, a single-ended input signal entering the HF channel is split into a differential signal via the inverter

gate at the input. The following capacitor-resistor networks differentiate the signal into transient pulses, which

then are converted into CMOS levels by a comparator. The transient pulses at the input of the comparator can

to 1 or 1 to 0. The comparator threshold is adjusted based on the expected bit transition. A decision logic (DCL)

at the output of the HF channel comparator measures the durations between signal transients. If the duration

between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the

DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel.

8.2 Functional Block Diagram

Figure 15. Conceptual Block Diagram of a Digital Capacitive Isolator

Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these

signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a

sufficiently high frequency, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter

(LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output

multiplexer.

12

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