10 mils

10 mils

40 mils

FR-4

Keep this

space free

from planes,

traces , pads,

and vias

Ground plane

Power plane

Low-speed traces

High-speed traces

ISO7330C, ISO7330FC, ISO7331C, ISO7331FC

SLLSEK9B – JANUARY 2015 – REVISED APRIL 2015

www.ti.com

11 Layout

11.1 PCB Material

For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of

up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the

requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower

dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self-

extinguishing flammability-characteristics.

11.2 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 23). Layer stacking should

be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency

signal layer.

•

Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their

inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits

of the data link.

•

Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for

transmission line interconnects and provides an excellent low-inductance path for the return current flow.

•

Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

•

Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the

stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the

power and ground plane of each power system can be placed closer together, thus increasing the high-frequency

bypass capacitance significantly.

For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide.

11.3 Layout Example

Figure 23. Recommended Layer Stack

20

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