DocID027506 Rev 2

13/49

MIS2DH

Mechanical and electrical specifications

49

2.4

Communication interface characteristics

2.4.1

SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Figure 3. SPI slave timing diagram

1. When no communication is ongoing, data on SDO is driven by internal pull-up resistors.

Note:

Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output

ports.

Table 6. SPI slave timing values

Symbol

Parameter

Unit

Min

Max

SPI clock cycle

100

ns

SPI clock frequency

10

MHz

CS setup time

5

ns

CS hold time

20

SDI input setup time

5

SDI input hold time

15

SDO valid output time

50

SDO output hold time

5

SDO output disable time

50

1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not

tested in production.