AS5147P-HTST datasheet(13/40 Pages) AMSCO

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ams Datasheet

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[v1-01] 2015-May-12

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AS5147P − Detailed Description

Figure 13:

SPI Timing

SPI Transaction

An SPI transaction consists of a 16-bit command frame followed

by a 16-bit data frame. Figure 14 shows the structure of the

command frame.

Figure 14:

SPI Command Frame

To increase the reliability of communication over the SPI, an

even parity bit (PARC) must be generated and sent. A wrong

setting of the parity bit causes the PARERR bit in the error flag

command frame. The 16-bit command specifies whether the

transaction is a read or a write and the address. Figure 15 shows

the read data frame.

Parameter

Description

Min

Max

Units

Time between CSn falling edge and CLK rising edge

350

tclk

Serial clock period

100

tclkL

Low period of serial clock

tclkH

High period of serial clock

Time between last falling edge of CLK and rising

edge of CSn

tclk/2

tCSn

High time of CSn between two transmissions

350

tMOSI

Data input valid to falling clock edge

tMISO

CLK edge to data output valid

tOZ

Release bus time after CS rising edge.

Bit

Name

Description

PARC

Parity bit (even) calculated on the command frame

R/W

0: Write

1: Read

13:0

ADDR

Address to read or write

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