EM341-RTR datasheet(50/237 Pages) SILABS

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EM341

Rev 1.0

Note: An application must disable all debug SWJ debug functionality to reclaim any of the four GPIOs: PC0, PC2, PC3, and

PC4. Disabling SWJ debug functionality prevents external debug tools from operating, including flash programming and

high-level debug tools.

Disabling the SWJ debugger interface is accomplished by setting the GPIO_DEBUGDIS bit in the GPIO_DBGCFG

SWJ debugger interface is already active, the bit GPIO_DEBUGDIS cannot be set. When GPIO_DEBUGDIS is

set, the SWJ debugger interface can be reclaimed by activating the SWJ while the EM341 is held in reset. If the

SWJ debugger interface is forced active in this manner, the bit GPIO_FORCEDBG is set in the GPIO_DBGSTAT

port’s CRTL/STAT register in the SWJ, is set high by an external debug tool.

7.4. Reset

A full chip reset is one due to power on (low or high voltage), the nRESET pin, the watchdog, or the

SYSRESETREQ bit. A full chip reset affects the GPIO configuration as follows:



The GPIO_PxCFGH/L configurations of all pins are configured as floating inputs.



The GPIO_EXTREGEN bit is set in the GPIO_DBGCFG register, which overrides the normal configuration

for PA7.



The GPIO_DEBUGDIS bit in the GPIO_DBGCFG register is cleared, allowing Serial Wire/JTAG access to

override the normal configuration of PC0, PC2, PC3, and PC4.

7.5. Boot Configuration

nBOOTMODE is a special alternate function of PA5 that is active only during a pin reset (nRESET) or a power-on-

reset of the always-powered domain (POR HV). If nBOOTMODE is asserted (pulled or driven low) when coming

out of reset, the processor starts executing an embedded serial-link-only monitor instead of its normal program.

While in reset and during the subsequent power-on-reset startup delay (512 OSCHF clocks), PA5 is automatically

configured as an input with a pull-up resistor. At the end of this time, the EM341 samples nBOOTMODE: a high

level selects normal boot mode, and a low level selects the embedded monitor. Figure 7.2 shows the timing

parameters for invoking monitor mode from a pin (nRESET) reset. Because OSCHF is running uncalibrated during

the reset sequence, the time for 512 OSCHF clocks may vary as indicated.

Figure 7.2. nBOOTMODE and nRESET Timing

Timing for a power-on-reset is similar except that OSCHF does not begin oscillating until up to 70 µsec after both

core and HV supplies are valid. Combined with the maximum 250 µsec allowed for HV to ramp from 0.5 V to 1.7 V,

an additional 320 µsec may be added to the 512 OSCHF clocks until nBOOTMODE is sampled.

If the monitor mode is selected (nBOOTMODE is low after 512 clocks), the FIB monitor software begins execution.

In order to filter out inadvertent jumps into the monitor, the FIB monitor re-samples the nBOOTMODE signal after a

3 ms delay. If the signal is still low, then the device stays in monitor mode. If the signal is high, then monitor mode

. . .

nRESET

OSCHF

. . .

nBOOTMODE

µsec min

. . .

512 clocks;

µsec min – 85 µsec max

nBOOTMODE Sampled;

FIB Monitor mode entered

nBOOTMODE Sampled by

FIB Monitor code

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