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EM341-RTR 数据表(PDF) 51 Page - Silicon Laboratories

部件名 EM341-RTR
功能描述  High-Performance, Integrated RF4CE System-on-Chip
PDF  237 Pages
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制造商  SILABS [Silicon Laboratories]
网页  http://www.silabs.com
标志 SILABS - Silicon Laboratories

EM341-RTR 数据表(HTML) 51 Page - Silicon Laboratories

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EM341
52
Rev 1.0
is exited and the normal program begins execution. In summary, the nBOOTMODE signal must be held low for
4 ms in order to properly invoke the FIB monitor.
After nBOOTMODE has been sampled, PA5 is configured as a floating input like the other GPIO configurations.
The GPIO_BOOTMODE bit in the GPIO_DBGSTAT register captures the state of nBOOTMODE so that software
may act on this signal if required.
Note: To avoid inadvertently asserting nBOOTMODE, PA5’s capacitive load may not exceed 250 pF.
7.6. GPIO Modes
7.6.1. Analog Mode
Analog mode enables analog functions, and disconnects a pin from the digital input and output logic. Only the
following GPIO pins have analog functions:

PA4, PA5, PB5, PB6, PB7, and PC1 can be analog inputs to the ADC.

PB0 can output the internal analog voltage reference from the ADC.

PC6 and PC7 can connect to an optional 32.768 kHz crystal.
Note: When an external timing source is required, a 32.768 kHz crystal is commonly connected to PC6 and PC7. Alternatively,
when PC7 is configured as a digital input, PC7 can accept a digital external clock input.
When configured in analog mode:

The output drivers are disabled.

The internal pull-up and pull-down resistors are disabled.

The Schmitt trigger input is connected to a high logic level.

Reading GPIO_PxIN returns a constant 1.
7.6.2. Input Mode
Input mode is used both for general purpose input and for on-chip peripheral inputs. Input floating mode disables
the internal pull-up and pull-down resistors, leaving the pin in a high-impedance state. Input pull-up or pull-down
mode enables either an internal pull-up or pull-down resistor based on the GPIO_PxOUT register. Setting a bit to 0
in GPIO_PxOUT enables the pull-down and setting a bit to 1 enables the pull up.
When configured in input mode:

The output drivers are disabled.

An internal pull-up or pull-down resistor may be activated depending on GPIO_PxCFGH/L and
GPIO_PxOUT.

The Schmitt trigger input is connected to the pin.

Reading GPIO_PxIN returns the input at the pin.

The input is also available to on-chip peripherals.
7.6.3. Output Mode
Output mode provides a general purpose output under direct software control. Regardless of whether an output is
configured as push-pull or open-drain, the GPIO’s bit in the GPIO_PxOUT register controls the output. The
GPIO_PxSET and GPIO_PxCLR registers can atomically set and clear bits within GPIO_PxOUT register. These
set and clear registers simplify software using the output port because they eliminate the need to disable interrupts
to perform an atomic read-modify-write operation of GPIO_PxOUT.
When configured in output mode:

The output drivers are enabled and are controlled by the value written to GPIO_PxOUT:

In open-drain mode: 0 activates the N-MOS current sink; 1 tri-states the pin.

In push-pull mode: 0 activates the N-MOS current sink; 1 activates the P-MOS current source.

The internal pull-up and pull-down resistors are disabled.

The Schmitt trigger input is connected to the pin.

Reading GPIO_PxIN returns the input at the pin.
Note: Reading GPIO_PxOUT returns the last value written to the register.
Depending on configuration and usage, GPIO_PxOUT and GPIO_PxIN may not have the same value.



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