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EM341-RTR 数据表(PDF) 171 Page - Silicon Laboratories

部件名 EM341-RTR
功能描述  High-Performance, Integrated RF4CE System-on-Chip
PDF  237 Pages
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制造商  SILABS [Silicon Laboratories]
网页  http://www.silabs.com
标志 SILABS - Silicon Laboratories

EM341-RTR 数据表(HTML) 171 Page - Silicon Laboratories

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EM341
172
Rev 1.0
10.1. Setup and Configuration
To use the ADC follow this procedure, described in more detail in the next sections:

Configure any GPIO pins to be used by the ADC in analog mode.

Set the offset and gain values.

If using DMA, reset the ADC DMA, define the DMA buffer, and start the DMA in the proper transfer mode.

If interrupts will be used, configure the top-level and second-level ADC interrupt bits.

Write the ADC configuration register to define the inputs, sample time, and start the conversions.
10.1.1. GPIO Usage
A GPIO pin used by the ADC as an input or voltage reference must be configured in analog mode by writing 0 to its
4-bit field in the proper GPIO_PxCFGH/L register. Note that a GPIO pin in analog mode cannot be used for any
digital functions, and GPIO_PxIN always reads it as 1. Only certain pins can be configured in analog mode. These
are listed in Table 10.1.
See "7. GPIO (General Purpose Input/Output)" on page 48 for more information about how to configure GPIO.
10.1.2. Voltage Reference
The ADC voltage reference (VREF) may optionally be output on PB0. To output the internal VREF on PB0, the
ADC must be enabled (ADC_ENABLE bit set in the ADC_CFG register) and PB0 must be configured in analog
mode.
Table 10.1. ADC GPIO Pin Usage
Analog Signal
GPIO
Configuration control
ADC0 input
PB5
GPIO_PBCFGH[7:4]
ADC1 input
PB6
GPIO_PBCFGH[11:8]
ADC2 input
PB7
GPIO_PBCFGH[15:12]
ADC3 input
PC1
GPIO_PCCFGL[7:4]
ADC4 input
PA4
GPIO_PACFGH[3:0]
ADC5 input
PA5
GPIO_PACFGH[7:4]
VREF output
PB0
GPIO_PBCFGL[3:0]



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