EM3587-RTR datasheet(29/59 Pages) SILABS

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EM358x

Rev 1.0

address space to software.

4.1.2. Embedded Memory

Embedded memory consists of flash memory and RAM.

The EM358x provides a total of either 256 or 512 kB of flash memory. The flash memory is provided in three

separate blocks:



Main Flash Block (MFB)



Fixed Information Block (FIB)



Customer Information Block (CIB)

The EM358x has either 32 or 64 kB of static RAM on-chip. Although the ARM® CortexTM-M3 allows bit band

accesses to this address region, the standard MPU configuration does not permit use of the bit-band feature. The

RAM is physically connected to the AHB System bus and is therefore accessible to both the ARM® CortexTM-M3

microprocessor and the debugger. The radio (802.15.4-2003 MAC), general purpose ADC, USB device controller,

and the two serial controllers are equipped with DMA controllers, which allow them to transfer data into and out of

RAM autonomously.

4.2. Interrupt System

The EM358x’s interrupt system is composed of two parts: a standard ARM® CortexTM-M3 Nested Vectored

Interrupt Controller (NVIC) that provides top-level interrupts, and a proprietary Event Manager (EM) that provides

second-level interrupts. The NVIC and EM provide a simple hierarchy. All second-level interrupts from the EM feed

into top-level interrupts in the NVIC. This two-level hierarchy allows for both fine granular control of interrupt

sources and coarse granular control over entire peripherals, while allowing peripherals to have their own interrupt

vector.

Refer to chapter 3 in the

Ember EM358x Reference Manual for more information.

4.2.1. Nested Vectored Interrupt Controller (NVIC)

The ARM® CortexTM-M3 Nested Vectored Interrupt Controller (NVIC) facilitates low-latency exception and interrupt

handling. The NVIC and the processor core interface are closely coupled, which enables low-latency interrupt

processing and efficient processing of late-arriving interrupts. The NVIC maintains knowledge of the stacked

(nested) interrupts to enable tail-chaining of interrupts. The NVIC also contains a software-configurable interrupt

prioritization mechanism.

4.2.2. Event Manager

The proprietary Event Manager provides second-level interrupts. The Event Manager takes a large variety of

hardware interrupt sources from the peripherals and merges them into a smaller group of interrupts in the NVIC.

Effectively, all second-level interrupts from a peripheral are “OR’d” together into a single interrupt in the NVIC. In

addition, the Event Manager provides missed indicators for the top-level peripheral interrupts with the register

INT_MISS.

4.2.3. Memory Protection Unit

The EM358x includes the ARM® CortexTM-M3 Memory Protection Unit, or MPU. The MPU controls access rights

and characteristics of up to eight address regions, each of which may be divided into eight equal sub-regions.

Refer to the ARM® CortexTM-M3 Technical Reference Manual (DDI 0337A) for a detailed description of the MPU.

4.3. Radio Module

The radio module consists of an analog front end and digital baseband.

Refer to chapter 4 in the

Ember EM358x Reference Manual for more information.

4.3.1. Receive (Rx) Path

The EM358x Rx path uses a low-IF, super-heterodyne receiver that rejects the image frequency using complex

mixing and polyphase filtering. The filtering within the Rx path improves the EM358x’s co-existence with other 2.4

GHz transceivers such as Zigbee/ 802.15.4-2003, IEEE 802.11-2007, and Bluetooth radios. The digital baseband

also provides gain control of the Rx path, both to enable the reception of small and large wanted signals and to

tolerate large interferers.

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