Data Sheet

ADP2230

SYNC PIN CONTROL SCHEMES

There are three possible switching control schemes for the

ADP2230 that can be selected using the SYNC pin: PWM

mode, PSM/PWM automatic transitioning mode, and external

clock synchronization. In PWM mode and PSM/PWM

automatic transitioning mode, the two bucks operate 180° out

of phase. When using the external clock synchronization

control scheme, the two bucks operate in phase.

PWM Mode

operates in the fixed 2 MHz PWM mode. When operating in

fixed frequency PWM mode, the duty cycle of the integrated

switches is adjusted to regulate the output voltage. The

switching frequency is 2 MHz, typical, over all input, output,

and load conditions.

At the start of each oscillator cycle in PWM, the P-channel

MOSFET switch is turned on, putting a positive voltage across

the inductor. Current in the inductor increases until the current

sense signal crosses the peak inductor current level that turns

off the P-channel MOSFET switch and turns on the N-channel

MOSFET synchronous rectifier. This puts a negative voltage

across the inductor, causing the inductor current to decrease.

The synchronous rectifier stays on until the next clock cycle.

PSM/PWM Automatic Transitioning Mode

is able to automatically transition between PWM mode and

PSM to maintain the highest efficiency. The ADP2230 operates

in fixed frequency PWM mode for medium to high load

currents. If the load current falls below the PSM/PWM

threshold level, the converter smoothly transitions to the

reduced frequency PSM. The PSM/PWM threshold varies with

the operating conditions. The PSM/PWM transition level for

various operating conditions is shown in Figure 8. The two

buck converters operate independently and can have different

PSM/PWM current thresholds for the same output voltage.

When the device enters PSM, the ADP2230 switches only when

necessary to maintain the output voltage within regulation.

When the output voltage falls below the lower regulation

threshold, the ADP2230 enters PWM mode for a few oscillator

cycles until the output voltage reaches the upper regulation

threshold. When it reaches the upper threshold, the ADP2230

enters sleep mode and waits for the output voltage to fall below

the lower regulation threshold. During the wait time between

the bursts, both power switches are off to minimize quiescent

current, and the output capacitor supplies the entire load

current. Due to the PSM architecture, the output voltage ripple

in this mode is larger than the ripple in the PWM mode of

operation. Figure 29 shows the typical operation in PSM mode.

External Clock Synchronization

When a 1.5 MHz to 2.5 MHz external clock is applied to the

SYNC pin, the ADP2230 automatically detects the rising edge

of the first clock and synchronizes to the external clock. If the

device is synchronized to an external clock, the two bucks

operate in phase, PSM is disabled, and the device is forced to

operate in PWM mode only.

FEATURES DESCRIPTIONS

Precision Enable

The ADP2230 has two enable inputs, EN1 and EN2, that allow

each of the buck outputs to be enabled and shut down inde-

pendently. The enable circuits of the ADP2230 minimize the

input current during shutdown and simultaneously provide

precision enable thresholds. When the enable input voltages are

below 0.4 V, the regulators are in shutdown mode. When both

buck converters are in shutdown mode, the supply current is

0.1 μA (typical). As the enable input voltages rise above the

standby enable threshold of 1.15 V (minimum), the internal

bias currents and voltages are activated, turning on the

precision enable circuitry. This allows the precision enable

circuitry to accurately detect when the ENx pin voltage exceeds

the precision enable rising threshold of 1.2 V (maximum).

Due to device constraints, EN1 and EN2 have different

operating maximums. EN2 has a 6.5 V operating maximum and

can be directly connected to VINx for any application. EN1 has

a 5.5 V operating maximum and cannot be directly connected

Connect a resistor divider from VINx to EN1 to reduce the

voltage applied to the EN1 pin to 5.5 V or less.

Quick Output Discharge

The ADP2230 includes an internal, 200 Ω discharge resistor on

the SWx pin that forces the output voltage to zero when the

buck is disabled. This ensures that the output of the buck is

always in a well defined state.

Output Short-Circuit Protection

The ADP2230 includes frequency foldback to prevent output

current runaway on a hard short. When the voltage at the

feedback pin (FBx) falls below 0.3 V, indicating the possibility of

a hard short at the output, the switching frequency is reduced to

half of the internal oscillator frequency. The reduction in the

switching frequency provides more time for the inductor to

discharge, preventing a runaway of output current.

Undervoltage Lockout

To protect against battery discharge, an undervoltage lockout

(UVLO) circuit is incorporated into the ADP2230. When the

input voltage drops below the UVLO threshold, the ADP2230

shuts down, and both power switches and both synchronous

rectifiers turn off. If EN1 and EN2 are logic high, when the

input voltage rises above the UVLO threshold, the soft start

periods are initiated and the two buck converters are enabled.

Rev. A | Page 13 of 18