Data Sheet

ADP2230

Rev. A | Page 17 of 18

PCB LAYOUT CONSIDERATIONS

For high efficiency, good regulation, and stability with the

ADP2230, a well designed PCB is required. Poor layout can

affect the ADP2230 buck performance, causing electromagnetic

interference (EMI), poor electromagnetic compatibility (EMC),

ground bounce, and voltage losses.

Improve heat dissipation from the package by increasing

the amount of copper attached to the pins of the ADP2230.

Use the following guidelines when designing PCBs:



Keep the low ESR input and output capacitors, CIN and

COUT, and the inductors, L1 and L2, as close as possible to

the ADP2230. Avoid long trace lengths from the device to

the capacitors that add series inductance and may cause

instability or increased ripple.



Route the output voltage path away from the inductor and

SWx node to minimize noise and magnetic interference.



Keep high current traces as short and as wide as possible.



Avoid routing high impedance traces near any node

connected to SWx or near the inductor to prevent radiated

noise injection.



Use a ground plane with several vias connected to the

component side ground to reduce noise interference on

sensitive circuit nodes.



The use of 0402 or 0603 capacitors achieves the smallest

possible footprint solution where board area is limited.

Figure 34. PCB Layout, Top

Figure 35. PCB Layout, Bottom