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LAN9500AI 数据表(PDF) 194 Page - Microchip Technology |
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LAN9500AI 数据表(HTML) 194 Page - Microchip Technology |
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194 / 213 page ![]() LAN950x DS00001875A-page 194 2010 - 2015 Microchip Technology Inc. Note 8-7 This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down and pull-up resistors add +/- 50uA per-pin (typical). Note 8-8 This is the total 5.5V input leakage for the entire device. Note 8-9 XI can optionally be driven from a 25MHz single-ended clock oscillator. Note 8-10 Measured at line side of transformer, line replaced by 100 Ω (+/- 1%) resistor. Note 8-11 Offset from 16nS pulse width at 50% of pulse peak. Note 8-12 Measured differentially. Note 8-13 Min/max voltages guaranteed as measured with 100 Ω resistive load. TABLE 8-13: 100BASE-TX TRANSCEIVER CHARACTERISTICS Parameter Symbol MIN TYP MAX Units Notes Peak Differential Output Voltage High VPPH 950 - 1050 mVpk Note 8-10 Peak Differential Output Voltage Low VPPL -950 - -1050 mVpk Note 8-10 Signal Amplitude Symmetry VSS 98 - 102 % Note 8-10 Signal Rise and Fall Time TRF 3.0 - 5.0 nS Note 8-10 Rise and Fall Symmetry TRFS -- 0.5 nS Note 8-10 Duty Cycle Distortion DCD 35 50 65 % Note 8-11 Overshoot and Undershoot VOS -- 5 % Jitter 1.4 nS Note 8-12 TABLE 8-14: 10BASE-T TRANSCEIVER CHARACTERISTICS Parameter Symbol MIN TYP MAX Units Notes Transmitter Peak Differential Output Voltage VOUT 2.2 2.5 2.8 V Note 8-13 Receiver Differential Squelch Threshold VDS 300 420 585 mV |
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