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LAN9500AI 数据表(PDF) 198 Page - Microchip Technology |
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LAN9500AI 数据表(HTML) 198 Page - Microchip Technology |
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198 / 213 page  LAN950x DS00001875A-page 198 2010 - 2015 Microchip Technology Inc. 8.5.4 EEPROM TIMING The following specifies the EEPROM timing requirements for the device: FIGURE 8-4: EEPROM TIMING TABLE 8-17: EEPROM TIMING VALUES Symbol Description MIN TYP MAX Units tckcyc EECLK Cycle time 1110 1130 ns tckh EECLK High time 550 570 ns tckl EECLK Low time 550 570 ns tcshckh EECS high before rising edge of EECLK 1070 ns tcklcsl EECLK falling edge to EECS low 30 ns tdvckh EEDO valid before rising edge of EECLK 550 ns tckhdis EEDO disable after rising edge EECLK 550 ns tdsckh EEDI setup to rising edge of EECLK 90 ns tdhckh EEDI hold after rising edge of EECLK 0 ns tckldis EECLK low to data disable (OUTPUT) 580 ns tcshdv EEDIO valid after EECS high (VERIFY) 600 ns tdhcsl EEDIO hold after EECS low (VERIFY) 0 ns tcsl EECS low 1070 ns EECLK EEDO EEDI EECS tckldis tcshckh EEDI (VERIFY) tckh tckl tckcyc tcklcsl tcsl tdvckh tckhdis tdsckh tdhckh tdhcsl tcshdv |
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