USB2250/50i/51/51i

DS00002005A-page 30

 2009 - 2015 Microchip Technology Inc.

7.3

Default Configuration Option

The Microchip device can be configured via its internal default configuration. Please see Section 7.2.2, "EEPROM Data

Descriptor" for specific details on how to enable default configuration. Please refer to Table 7-1 for the internal default

values that are loaded when this option is selected.

7.3.1

EXTERNAL HARDWARE NRESET

A valid hardware reset is defined as assertion of nRESET for a minimum of 1

s after all power supplies are within oper-

ating range. While reset is asserted, the device (and its associated external circuitry) consumes less than 500

A of

current.

Assertion of nRESET (external pin) causes the following:

1.

The PHY is disabled and the differential pair will be in a high-impedance state.

2.

All transactions immediately terminate; no states are saved.

3.

All internal registers return to the default state.

4.

The external crystal oscillator is halted.

5.

The PLL is halted.

6.

The processor is reset.

7.

All media interfaces are reset.

7.3.1.1

nRESET for EEPROM Configuration

FIGURE 7-1:

NRESET TIMING FOR EEPROM MODE

TABLE 7-2:

NRESET TIMING FOR EEPROM MODE

Name

Description

MIN

TYP

MAX

Units

t1

nRESET asserted

1

sec

t2

Device recovery/stabilization

500

sec

t3

8051 programs device configuration

20

50

msec

t4

USB attach

100

msec

t5

Host acknowledges attach and signals USB reset

100

msec

t6

USB idle

Undefined

msec

t7

Ready to handle requests (with or without data)

5

msec

Note:

All power supplies must have reached the operating levels mandated in Section 9.0, "DC Parameters",

prior to (or coincident with) the assertion of nRESET.

t1

t2

t4

t5

t6

t7

nRESET

VSS

Hardware

reset

asserted

Device

Recovery/

Stabilization

8051 Sets

Configuration

Registers

Attach

USB

Upstream

USB Reset

recovery

Idle

Start

completion

request

response

t3