 2009 - 2015 Microchip Technology Inc.

DS00002005A-page 10

USB2250/50i/51/51i

5.0

PIN DESCRIPTIONS

This section provides a detailed description of each signal. The signals are arranged in functional groups according to

their associated interface. The pin descriptions are applied when using the internal default firmware and can be refer-

enced in Section 7.0, "Configuration Options," on page 21. Please reference Section 1.1, "Acronyms," on page 5 for a

list of the acronyms used.

The “n” symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage

level. When “n” is not present in the signal name, the signal is asserted at the high voltage level.

The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of

“active low” and “active high” signals. The term assert, or assertion, indicates that a signal is active, independent of

whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inac-

tive.

5.1

128-Pin VTQFP Pin Descriptions

TABLE 5-1:

USB2250/50I/51/51I 128-PIN VTQFP PIN DESCRIPTIONS

Name

Symbol

128-Pin

VTQFP

Buffer

Type

Description

COMPACT FLASH (CF) INTERFACE

CF Chip Select 0

CF_nCS0

71

O12PU

This pin is the active low chip select 0 signal for

the task file registers of the CF ATA device in

True IDE mode. This pin has a weak internal

pull-up resistor.

CF Register

Address

CF_SA[2:0]

82

83

84

I/O12

These pins are the register select address bits

for the CF ATA device.

CF Interrupt

CF_IRQ

74

IPD

This is the active high interrupt request signal

from the CF device. This pin has a weak internal

pull-down resistor.

CF Data 15-8

CF_D[15:8] /

70

68

66

62

60

90

89

87

I/O12PD

CF_D[15:8]: These pins are the bi-directional

data signals CF_D15 - CF_D8 in True IDE mode

data transfer.

In True IDE mode, all task file register

operations occur on CF_D[7:0], while data

transfer occurs on CF_D[15:0].

These bi-directional data signals have weak

internal pull-down resistors.

CF Data 7-0

CF_D[7:0]

69

67

63

61

59

88

86

85

I/O12PD

CF_D[7:0]: These pins are the bi-directional

data signals CF_D7 - CF_D0 in True IDE mode

data transfer. In True IDE mode, all of the task

file register operations occur on CF_D[7:0],

while data transfer occurs on CF_D[15:0].

These bi-directional data signals have weak

internal pull-down resistors.

IO Ready

CF_IORDY

80

IPU

This pin is the active high input signal for

IORDY. This pin has a weak internal pull-up

resistor.

CF Card

Detection1

CF_nCD

58

I/O12

Designates as the Compact Flash card

detection pin.

CF Hardware

Reset

CF_RESET_N

79

O12

This pin is an active low hardware reset signal

to the CF device.

CF IO Read

CF_nIOR

72

O12

This pin is an active low read strobe signal for

the CF device.

CF IO Write

Strobe

CF_nIOW

73

O12

This pin is an active low write strobe signal for

the CF device.