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DS00001824A-page 9

USB375x

3.3

Timing Diagrams

3.3.1

UVLO AND OVLO TIMING

The timing diagram below shows the operation of the OVP switch as VBUS crosses the UVLO and OVLO thresholds.

The behavior of the INT_B signal is also shown in Figure 3-1 below.

3.3.2

AUTOMATIC CHARGER DETECTION TIMING

The timing diagrams below illustrate the automatic charger detection timing that is followed when implementing the

automatic charger detection flow charts shown in this section.

FIGURE 3-1:

UVLO AND OVLO TIMING

FIGURE 3-2:

CHARGER DETECTION TIMING SDP (USB3750-1)

INT_B

VBUS

VOUT

OVLO

UVLO

OVP switch

enabled

OVP switch

disabled

OVLO

Fall Int.

UVLO

OVLO

Start Chrg

Detection

OVP switch

disabled

OVLO Int.

VBUS

Con. Det. or

UVLO

VOUT

OVP Switch

Enable

Chrg Det

Finish

USB

X

Connect Detect

Check for SE1

Drive Vdat Source on DP

USB Mux

INT_B

Mux1 and Mux2 Disabled

Mux1 En.

SDP Detected

Mux1 En.