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USB3750 数据表(PDF) 20 Page - Microchip Technology

部件名 USB3750
功能描述  USB 2.0 Protection IC with Battery
PDF  31 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

USB3750 数据表(HTML) 20 Page - Microchip Technology

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USB375x
DS00001824A-page 20
 2011 - 2014 Microchip Technology Inc.
4.4.4
REG 0: STATUS REGISTER
This register indicates the current status of the USB375x.
.
4.4.5
REG 1: CONFIGURATION REGISTER
Field Name
Bit
Access
Default
Description
OVLO Status
0
rd
0
Over Voltage Lockout Comparator Status. Set to 0b
when VBUS goes above the OVLO threshold.
OVLO Latch
1
rd
0
Set to 1b when an unmasked OVLO interrupt occurs
on OVLO Status. Auto cleared when this register is
read.
OVP SwitchStatus
2
rd
0
Indicates the status of the OVP switch. A 0b indicates
the OVP switch is closed. A 1b indicates that the OVP
switch is open.
CurrentLimitStatus
3
rd
0
Indicates the status of the 100mA Current Limit. A 1b
indicates that the current limit is enabled.
ChrgDetComplete
4
rd
0
A 1b Indicates Charger Detection has completed.
ChargerType
7:5
rd
000
This register indicates the result of the automatic
charger detection.
000 = ChargerDetection is not complete
001 = DCP
010 = CDP
011 = SDP
100 = SE1 Low Current Charger
101 = SE1 High Current Charger
If EnhancedChrgDet = 0 the USB375x is unable to
distinguish between a DCP and a CDP and will return
DCP as the ChargerType.
Field Name
Bit
Access
Default
Description
EnableOVP Switch
0
r/w
0
The OVP switch will be enabled when this bit is set to
1b.
EnableCurrentLimit
1
r/w
0
Controls the 100mA current limit block. The 100mA
current limit will be enabled when this bit is set to 1b
and the OverrideCurrentLimit bit is also set to 1b.
OverideVBUS
2
r/w
0
When this bit is set to 1b the OVP switch is controlled
by the EnableOVP Switch bit.
OverrideCurrentLimit
3
r/w
0
When this bit is set to 1b the current limit is controlled
by the EnableCurrentLimit bit.
Reserved
4
r/w
0
Reserved
EnableMux1
5
r/w
1
When this bit is set to 1b the Mux 1 path is enabled
(USB3750 Only)
EnableMux2
6
r/w
0
When this bit is set to 1b the Mux 2 path is enabled
(USB3750 Only)
SoftPOR
7
r/w
0
Hardware reset. When this bit is set to 1b, the
USB375x will reset and restart the POR sequence.
This bit will autoclear in TSOFT_POR. The USB375x
registers should not be accessed until the TSOFT_POR
time has expired.



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