USB375x

DS00001824A-page 18

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During power-up and charger detection the USB Mux switches will be disabled regardless of the EnableMux1 and

EnableMux2 settings.

Once power-up and charger detection are complete EnableMux1 is enabled by default.

4.4

USB375x Registers

4.4.1

If the USB375x has a change in status it can assert the INT_B by pulling this line to ground. The USB375x INT_B line

will stay low and then auto-clear after 1mS or until cleared by reading the Status Register. This prevents INT_B from

face.

operations.

SDA, and INT_B are open collector when configured as an output. This requires an external pull-up resistor on SDA

and INT_B.

current limit is enabled. Only devices that draw <100mA will be enabled through the path as part of dead battery provi-

sion support. In order to bypass this limit, bits 0 (EnableOVP Switch) and 2 (OverideVBUS) in Register 1 (Configuration

4.4.2

4.4.2.1

The slave supports two types of reads, single reads, and continuous reads. In a single read the master asserts a NACK

after the first read data. The format for a single read is shown in Figure 4-7. The read command has three phases. These

three phases are device address phase, register address phase, and read data phase. Each phase is terminated by an

ACK or NACK. The device address phase consists of the 7-bit slave address followed by a '1' to indicate a read. If the

address matches the slave's address then the slave drives an ACK. The register address phase consists of an 8-bit

register address. The slave will always ACK the register address. In the data phase the slave will return the register read

data. If the register address was a valid register than the slave will return the data, otherwise it will return 0xFF.

The continuous read command is similar to the single read command, however after the read data the master will drive

an ACK and then provide another register address. The master will then wait for the read data as shown in Figure 4-8.

The continuous read is terminated by the master by driving a NACK after the last read data and then asserting a STOP

condition.

FIGURE 4-7:

ACK

Register Addr X

7-bit Slave ID

R/W

7-bit Slave ID

ACK

R/W

P

P

Driven By

Master

Driven By

Slave

S

S

1

0

NACK

ACK

Register X Value