Application information

R7986A

16/37

DocID026997 Rev 1

and:

Equation 8

the internal PDMOS.

The peak-to-peak voltage across the input capacitor can be calculated as:

Equation 9

where ESR is the equivalent series resistance of the capacitor.

Given the physical dimension, ceramic capacitors can well meet the requirements of the

input filter sustaining a higher input RMS current than electrolytic/tantalum types. In this

Equation 10

neglecting the small ESR of ceramic capacitors.

Considering

= 1, this function has its maximum in D = 0.5, therefore, given the maximum

Equation 11

In Table 6 some multi-layer ceramic capacitors suitable for this device are reported:

A ceramic bypass capacitor, as close to the VCC and GND pins as possible, so that

additional parasitic ESR and ESL are minimized, is recommended in order to prevent

instability on the output voltage due to noise. The value of the bypass capacitor can go from

100 nF to 1 µF.

Table 6. Input MLCC capacitors

Manufacture

Series

Cap value (

F)

Rated voltage (V)

Taiyo Yuden

UMK325BJ106MM-T

10

50

GMK325BJ106MN-T

10

35

Murata

GRM32ER71H475K

4.7

50

+

–

--------------------------------------

=



-------------------------

1

D



----

–



 D D



----

1D

–





+





+



=



---------------------------

1

D



----

–



 D D



----

1D

–





+





=



------------------------------------------------

=