R7986ATR datasheet(25/37 Pages) STMICROELECTRONICS

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DocID026997 Rev 1

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R7986A

Application information

The guidelines for positioning the poles and the zeroes and for calculating the component

values can be summarized as follows:

Choose a value for R1, usually between 1 k and 5 k, in order to have values of C4

and C5 not comparable with parasitic capacitance of the board.

Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:

Equation 30

where fESR is the ESR zero:

Equation 31

and Vs is the sawtooth amplitude. The voltage feed-forward keeps the ratio Vs/Vin constant.

Calculate C4 by placing the zero one decade below the output filter double pole:

Equation 32

Then calculate C3 in order to place the second pole at four times the system bandwidth

(BW):

Equation 33

For example with VOUT = 5 V, VIN = 24 V, IO = 3 A, L = 18 H, COUT = 330 F, and

ESR = 35 m

 the Type II compensation network is:

In Figure 15, the module and phase of the open loop gain is shown. The bandwidth is about

21 kHz and the phase margin is 45°.

fESR

fLC

------------





fESR

------------

VIN

--------- R1





fESR

 ESR C

OUT



--------------------------------------------

 R

4 fLC



-------------------------------

 R

4 C4 4BW



–



--------------------------------------------------------------

R1 1.1k

R2 150

R4 4.99k

C4 82nF

C5 68pF





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